Abstract: One or more systems, devices, or methods of use provided herein relate to a process of long-range coupling qubits in a quantum computing device with energy loss protection. A system can comprise a first transmon coupler capable of selectively coupling a first tunable coupler qubit to a first fluxonium qubit; a second transmon coupler capable of selectively coupling a second tunable coupler qubit to a second fluxonium qubit. Additionally, in one or more embodiments, the system can include a long-range coupler capable of selectively coupling the first fluxonium qubit to the second fluxonium qubit. The first transmon coupler can be coupled to a first B mode of the first tunable coupler qubit, and the second transmon coupler can be coupled to a second B mode of the second tunable coupler qubit.

Abstract: Techniques for designing and fabricating quantum circuitry, including a coplanar waveguide (CPW), for quantum applications are presented. With regard to a CPW, a central conductor and two return conductor lines can be formed on a dielectric substrate, with one return conductor line on each side of the central conductor and separated from it by a space. The central conductor can have bridge portions that can be raised a desired distance above the substrate and base conductor portions situated between the bridge portions and in contact with the surface of the substrate; and/or portions of the substrate underneath the bridge portions of the central conductor can be removed such that the bridge portions, whether raised or unraised, can be the desired distance above the surface of the remaining substrate, and the base conductor portions can be in contact with other portions of the surface of the substrate that were not removed.

Abstract: Techniques regarding methods and/or apparatuses for protecting metal substrates during one or more lithography processes are provided. For example, one or more embodiments described herein can comprise a method that can include coating a metal substrate with a polymer film that self-assembles on a metal oxide positioned on a surface of the metal substrate. The method can also include covalently bonding the polymer film to the metal oxide.

Abstract: A device comprises a first superconducting quantum bit, a second superconducting quantum bit, and a coupler circuit. The first superconducting quantum bit comprises a superconducting tunnel junction and a shunt inductor which form a first superconducting loop. The second superconducting quantum bit comprises a superconducting tunnel junction and a shunt inductor which form a second superconducting loop. The coupler circuit is coupled between the first and second superconducting quantum bits. The coupler circuit is configured to implement an entanglement gate operation between the first and second superconducting quantum bits through exchange interactions between the coupler circuit and the first superconducting quantum bit and the second superconducting quantum bit, when the coupler circuit is driven by a control signal.

Abstract: Techniques for trapping quasiparticles in superconductor devices are provided. A superconductor device can comprise a substrate layer. The superconductor device can further comprise a first superconductor layer composed of a first superconductor material, on a first surface of a substrate layer. The superconductor device can further comprise a trapping material buried in the first superconductor layer, wherein the trapping material is formulated to trap quasiparticles.

Abstract: Techniques regarding methods and/or apparatuses for protecting metal substrates during one or more lithography processes are provided. For example, one or more embodiments described herein can comprise a method that can include coating a metal substrate with a polymer film that self-assembles on a metal oxide positioned on a surface of the metal substrate. The method can also include covalently bonding the polymer film to the metal oxide.

Abstract: Techniques for designing and fabricating quantum circuitry, including a coplanar waveguide (CPW), for quantum applications are presented. With regard to a CPW, a central conductor and two return conductor lines can be formed on a dielectric substrate, with one return conductor line on each side of the central conductor and separated from it by a space. The central conductor can have bridge portions that can be raised a desired distance above the substrate and base conductor portions situated between the bridge portions and in contact with the surface of the substrate; and/or portions of the substrate underneath the bridge portions of the central conductor can be removed such that the bridge portions, whether raised or unraised, can be the desired distance above the surface of the remaining substrate, and the base conductor portions can be in contact with other portions of the surface of the substrate that were not removed.

Abstract: Techniques for trapping quasiparticles in superconductor devices are provided. A superconductor device can comprise a substrate layer. The superconductor device can further comprise a first superconductor layer composed of a first superconductor material, on a first surface of a substrate layer. The superconductor device can further comprise a trapping material buried in the first superconductor layer, wherein the trapping material is formulated to trap quasiparticles.

Abstract: A field effect transistor including a dielectric layer on a substrate, a nano-structure material (NSM) layer on the dielectric layer, a source electrode and a drain electrode formed on the NSM layer, a gate dielectric formed on at least a portion of the NSM layer between the source electrode and the drain electrode, a T-shaped gate electrode formed between the source electrode and the drain electrode, where the NSM layer forms a channel of the FET, and a doping layer on the NSM layer extending at least from the sidewall of the source electrode to a first sidewall of the gate dielectric, and from a sidewall of the drain electrode to a second sidewall of the gate dielectric.

Abstract: In one aspect, a method for placing carbon nanotubes on a dielectric includes: using DSA of a block copolymer to create a pattern in the placement guide layer on the dielectric which includes multiple trenches in the placement guide layer, wherein there is a first charge on sidewall and top surfaces of the trenches and a second charge on bottom surfaces of the trenches, and wherein the first charge is different from the second charge; and depositing a carbon nanotube solution onto the dielectric, wherein self-assembly of the deposited carbon nanotubes within the trenches occurs based on i) attractive forces between the first charge on the surfaces of the carbon nanotubes and the second charge on the bottom surfaces of the trenches and ii) repulsive forces between the first charge on the surfaces of the carbon nanotubes and the first charge on sidewall and top surfaces of the trenches.

Abstract: In one aspect, a method for placing carbon nanotubes on a dielectric includes: using DSA of a block copolymer to create a pattern in the placement guide layer on the dielectric which includes multiple trenches in the placement guide layer, wherein there is a first charge on sidewall and top surfaces of the trenches and a second charge on bottom surfaces of the trenches, and wherein the first charge is different from the second charge; and depositing a carbon nanotube solution onto the dielectric, wherein self-assembly of the deposited carbon nanotubes within the trenches occurs based on i) attractive forces between the first charge on the surfaces of the carbon nanotubes and the second charge on the bottom surfaces of the trenches and ii) repulsive forces between the first charge on the surfaces of the carbon nanotubes and the first charge on sidewall and top surfaces of the trenches.

Abstract: In one aspect, a method for placing carbon nanotubes on a dielectric includes: using DSA of a block copolymer to create a pattern in the placement guide layer on the dielectric which includes multiple trenches in the placement guide layer, wherein there is a first charge on sidewall and top surfaces of the trenches and a second charge on bottom surfaces of the trenches, and wherein the first charge is different from the second charge; and depositing a carbon nanotube solution onto the dielectric, wherein self-assembly of the deposited carbon nanotubes within the trenches occurs based on i) attractive forces between the first charge on the surfaces of the carbon nanotubes and the second charge on the bottom surfaces of the trenches and ii) repulsive forces between the first charge on the surfaces of the carbon nanotubes and the first charge on sidewall and top surfaces of the trenches.

Abstract: In one aspect, a method for placing carbon nanotubes on a dielectric includes: using DSA of a block copolymer to create a pattern in the placement guide layer on the dielectric which includes multiple trenches in the placement guide layer, wherein there is a first charge on sidewall and top surfaces of the trenches and a second charge on bottom surfaces of the trenches, and wherein the first charge is different from the second charge; and depositing a carbon nanotube solution onto the dielectric, wherein self-assembly of the deposited carbon nanotubes within the trenches occurs based on i) attractive forces between the first charge on the surfaces of the carbon nanotubes and the second charge on the bottom surfaces of the trenches and ii) repulsive forces between the first charge on the surfaces of the carbon nanotubes and the first charge on sidewall and top surfaces of the trenches.

Abstract: A field effect transistor including a dielectric layer on a substrate, a nano-structure material (NSM) layer on the dielectric layer, a source electrode and a drain electrode formed on the NSM layer, a gate dielectric formed on at least a portion of the NSM layer between the source electrode and the drain electrode, a T-shaped gate electrode formed between the source electrode and the drain electrode, where the NSM layer forms a channel of the FET, and a doping layer on the NSM layer extending at least from the sidewall of the source electrode to a first sidewall of the gate dielectric, and from a sidewall of the drain electrode to a second sidewall of the gate dielectric.

Abstract: A field effect transistor including a dielectric layer on a substrate, a nano-structure material (NSM) layer on the dielectric layer, a source electrode and a drain electrode formed on the NSM layer, a gate dielectric formed on at least a portion of the NSM layer between the source electrode and the drain electrode, a T-shaped gate electrode formed between the source electrode and the drain electrode, where the NSM layer forms a channel of the FET, and a doping layer on the NSM layer extending at least from the sidewall of the source electrode to a first sidewall of the gate dielectric, and from a sidewall of the drain electrode to a second sidewall of the gate dielectric.

Abstract: A field effect transistor including a dielectric layer on a substrate, a nano-structure material (NSM) layer on the dielectric layer, a source electrode and a drain electrode formed on the NSM layer, a gate dielectric formed on at least a portion of the NSM layer between the source electrode and the drain electrode, a T-shaped gate electrode formed between the source electrode and the drain electrode, where the NSM layer forms a channel of the FET, and a doping layer on the NSM layer extending at least from the sidewall of the source electrode to a first sidewall of the gate dielectric, and from a sidewall of the drain electrode to a second sidewall of the gate dielectric.

Abstract: A method of modifying a wafer having a semiconductor disposed on an insulator is provided and includes forming pairs of semiconductor pads connected via respective nanowire channels at each of first and second regions with different initial semiconductor thicknesses and reshaping the nanowire channels into nanowires to each have a respective differing thickness reflective of the different initial semiconductor thicknesses.

Abstract: Non-planar semiconductor devices including at least one semiconductor nanowire having a tapered profile which widens from the source side of the device towards the drain side of the device are provided which have reduced gate to drain coupling and therefore reduced gate induced drain tunneling currents.

Abstract: A floating gate transistor, memory cell, and method of fabricating a device. The floating gate transistor includes one or more gated wires substantially cylindrical in form. The floating gate transistor includes a first gate dielectric layer at least partially covering the gated wires. The floating gate transistor further includes a plurality of gate crystals discontinuously arranged upon the first gate dielectric layer. The floating gate transistor also includes a second gate dielectric layer covering the plurality of gate crystals and the first gate dielectric layer.

Abstract: Techniques for defining a damascene gate in nanowire FET devices are provided. In one aspect, a method of fabricating a FET device is provided including the following steps. A SOI wafer is provided having a SOI layer over a BOX. Nanowires and pads are patterned in the SOI layer in a ladder-like configuration. The BOX is recessed under the nanowires. A patternable dielectric dummy gate(s) is formed over the recessed BOX and surrounding a portion of each of the nanowires. A CMP stop layer is deposited over the dummy gate(s) and the source and drain regions. A dielectric film is deposited over the CMP stop layer. The dielectric film is planarized using CMP to expose the dummy gate(s). The dummy gate(s) is at least partially removed so as to release the nanowires in a channel region. The dummy gate(s) is replaced with a gate conductor material.