Patents by Inventor SARVESWARA BADE

SARVESWARA BADE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Leakage current reduction in stacked field-effect transistors
    Patent number: 9673805
    Abstract: A method and system for reducing leakage current in a testing circuit are provided. Embodiments include a testing circuit that includes a digital buffer that includes a first transistor operatively coupled to a second transistor, where a drain of the first transistor is operatively coupled to a source of the second transistor. The second transistor is switched into cutoff mode. The digital buffer also includes a reference voltage generation circuit. The reference voltage generation circuit is operatively connected to the drain of the first transistor and the source of the second transistor. The reference voltage generation circuit is configured to reduce the leakage current in the digital buffer.
    Type: Grant
    Filed: August 21, 2014
    Date of Patent: June 6, 2017
    Assignee: International Business Machines Corporation
    Inventors: Sarveswara Bade, Shiu Chung Ho, Marcel A. Kossel, Pradeep Thiagarajan
  • LEAKAGE CURRENT REDUCTION IN STACKED FIELD-EFFECT TRANSISTORS
    Publication number: 20160056809
    Abstract: A method and system for reducing leakage current in a testing circuit are provided. Embodiments include a testing circuit that includes a digital buffer that includes a first transistor operatively coupled to a second transistor, where a drain of the first transistor is operatively coupled to a source of the second transistor. The second transistor is switched into cutoff mode. The digital buffer also includes a reference voltage generation circuit. The reference voltage generation circuit is operatively connected to the drain of the first transistor and the source of the second transistor. The reference voltage generation circuit is configured to reduce the leakage current in the digital buffer.
    Type: Application
    Filed: August 21, 2014
    Publication date: February 25, 2016
    Inventors: SARVESWARA BADE, SHIU CHUNG HO, MARCEL A. KOSSEL, PRADEEP THIAGARAJAN