Abstract: A circuit arrangement for limiting the gate current at a field effect transistor, FET, comprises a first FET and a DC supply network connected to a gate terminal of the first FET; ¬wherein the supply network provides a voltage Vgg to the gate terminal of the first FET via a first connection comprising a high impedance resistor R1 and a second FET connected in series therewith and having a gate terminal; the second FET having an ON state at a gate-source voltage of 0 V and having its gate terminal also connected to the gate terminal of the first FET via a second connection in parallel with the resistor R1; wherein a voltage drop occurring across the resistor R1 results in increasing blocking of the second FET.