Patents by Inventor Sascha Richter

Sascha Richter has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8375350
    Abstract: In one embodiment of the invention, a method is disclosed including executing one or more commands of a work script to perform work on a portion of a netlist of an integrated circuit design; receiving an indication of a program fault in a first integrated circuit (IC) design program performing work on the portion of the netlist in response to the one or more commands of the work script; and generating a debug work script associated with the work script in response to the program fault, the debug work script including an identification of the portion of the netlist of the integrated circuit design upon which work was being performed during the program fault.
    Type: Grant
    Filed: November 21, 2011
    Date of Patent: February 12, 2013
    Assignee: Cadence Design Systems, Inc.
    Inventors: Sascha Richter, Denis Baylor
  • Patent number: 8065640
    Abstract: In one embodiment of the invention, a method is disclosed including executing one or more commands of a work script to perform work on a portion of a netlist of an integrated circuit design; receiving an indication of a program fault in a first integrated circuit (IC) design program performing work on the portion of the netlist in response to the one or more commands of the work script; and generating a debug work script associated with the work script in response to the program fault, the debug work script including an identification of the portion of the netlist of the integrated circuit design upon which work was being performed during the program fault.
    Type: Grant
    Filed: May 30, 2007
    Date of Patent: November 22, 2011
    Assignee: Cadence Design Systems, Inc.
    Inventors: Sascha Richter, Denis Baylor
  • Patent number: 7945880
    Abstract: In one embodiment of the invention, a method of retiming a circuit is disclosed. The method includes computing an upper bound and a lower bound for a clock period of a clock signal to clock a circuit in response to a netlist of the circuit; selecting a potential clock period for the clock signal to clock registers of the circuit in response to the computed upper bound and the computed lower bound for the clock period; computing an upper bound and a lower bound of a retiming value for each node of the circuit to determine if a retiming of the circuit is achievable with the potential clock period; and computing the retiming value for each node of the circuit to minimize circuit area in response to the computed upper bound and the computed lower bound of the retiming value for each node.
    Type: Grant
    Filed: May 30, 2007
    Date of Patent: May 17, 2011
    Assignee: Cadence Design Systems, Inc.
    Inventors: Christoph Albrecht, Sascha Richter
  • Patent number: 7559040
    Abstract: In optimizing a design of an integrated circuit, an iteration of a logic optimization process is performed that at least partially optimizes a circuit design such that there is slack remaining in one or more combinational logic paths in the circuit design following the iteration. A clock latency scheduling process is performed that respectively distributes the remaining slack of one or more respective combinational logic paths in the circuit design across respective registers in the circuit design. Another iteration of the logic optimization process is performed that uses at least a portion of the distributed slack to further optimize the circuit design.
    Type: Grant
    Filed: March 10, 2006
    Date of Patent: July 7, 2009
    Assignee: Cadence Design Systems, Inc.
    Inventors: Christoph Albrecht, Andreas Kuehlmann, David Seibert, Sascha Richter