Patents by Inventor Sascha Siegler

Sascha Siegler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • FUSES AND FUSE PROGRAMMING METHODS
    Publication number: 20150228436
    Abstract: A fuse may be provided, which may include: a first fuse link; a second fuse link coupled in series to the first fuse link; and a connection element coupled between the first and second fuse links and disposed in the same level as the first and second fuse links.
    Type: Application
    Filed: January 30, 2015
    Publication date: August 13, 2015
    Inventors: Franz Ungar, Gunther Lehmann, Armin Fischer, Alexander Von Glasow, Sascha Siegler
  • Method for designing integrated circuits comprising replacement logic gates
    Patent number: 7685550
    Abstract: In a method for designing integrated circuits comprising replacement logic components, a plurality of logic cells and a plurality of filler cells which fill interspaces between the logic cells are positioned on a chip area. In this case, some or all of the filler cells represent replacement logic components for the integrated circuit and have been or are interconnected or wired in such a way that they form capacitances in the integrated circuit.
    Type: Grant
    Filed: February 24, 2006
    Date of Patent: March 23, 2010
    Assignee: Infineon Technologies AG
    Inventors: Sascha Siegler, Roswitha Deppe, Georg Georgakos
  • Clock control cell
    Patent number: 7274240
    Abstract: A clock control cell for production of an output clock signal from an input clock signal has a hold element and an output stage. The hold element is preceded by a signal level converter, with the signal level converter designed such that it converts an input signal to an output signal at predetermined signal levels, wherein the input clock signal is the input signal of the signal level converter.
    Type: Grant
    Filed: June 21, 2005
    Date of Patent: September 25, 2007
    Assignee: Infineon Technologies AG
    Inventors: Sascha Siegler, Gerhard Weber, Thomas Baumann, Stefan Bergler
  • Method for designing integrated circuits comprising replacement logic gates
    Publication number: 20060218517
    Abstract: In a method for designing integrated circuits comprising replacement logic components, a plurality of logic cells and a plurality of filler cells which fill interspaces between the logic cells are positioned on a chip area. In this case, some or all of the filler cells represent replacement logic components for the integrated circuit and have been or are interconnected or wired in such a way that they form capacitances in the integrated circuit.
    Type: Application
    Filed: February 24, 2006
    Publication date: September 28, 2006
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Sascha Siegler, Roswitha Deppe, Georg Georgakos
  • Clock control cell
    Publication number: 20060001468
    Abstract: A clock control cell for production of an output clock signal from an input clock signal has a hold element and an output stage. The hold element is preceded by a signal level converter, with the signal level converter designed such that it converts an input signal to an output signal at predetermined signal levels, wherein the input clock signal is the input signal of the signal level converter.
    Type: Application
    Filed: June 21, 2005
    Publication date: January 5, 2006
    Inventors: Sascha Siegler, Gerhard Weber, Thomas Baumann, Stefan Bergler