Abstract: A computing device comprising at least one processing module carrying multiple execution units each with a local memory unit; and a local network of the processing module linking at least some of the execution units to each other by respective communication paths; wherein the execution units are configured to execute a binary code segment at least temporarily stored in their respective associated local memory unit and derived from a computer executable program code application containing application code sections; and wherein at least one of the execution units is designated for executing a binary code segment as an assigned binary code segment based on a pre-determined runtime schedule with fixed time slots during which the execution unit is granted exclusive access to at least one of the communication paths when executing the assigned binary code segment in line with a pre-defined running order of the application code sections.

Abstract: A processing device for parallel computing and a corresponding method include processing units, a scheduler module, a first common data transmission element, and a first input interface. The first input interface is configured to receive a continuous first data stream and transmit the first data stream via the first common transmission element. Each of the processing units is connected to the first common transmission element and configured to receive data transmitted via the first common transmission element. The scheduler module is in electronic communication with each of the processing units and configured to assign parts of the first data stream to each of the processing units for simultaneous processing. Each of the processing units is configured to monitor the complete first data stream, select the parts of the first data stream assigned by the scheduler module, and perform processing operations on the selected parts of the first data stream.

Abstract: A method for multi-source communication for triple-modular redundancy (TMR), a method for branched communication, and a method for virtual buses are disclosed. A method includes a) transmitting by at least two different source nodes in each case at least two identical messages which contain at least flow control data, payload data and check data to at least one predetermined receive node where the messages reach the receive node together at a predetermined time, b) combining by the receive node the messages received by the receive node into a combined message containing flow control data, payload data and check data, or comparing by the receive node of messages received by the receive node, and c) further processing of the combined message by the receive node or further processing of at least one of the messages received by the receive node based on comparison from step b).

Abstract: A processor system comprises a memory having at least two interleaved memory banks, at least two multiplexers which are respectively coupled to one of the at least two interleaved memory banks via a respective memory bank bus, a first processor or processor core which is coupled to first multiplexer inputs of the at least two multiplexers via a first data bus, a second processor or processor core which is coupled to second multiplexer inputs of the at least two multiplexers via a second data bus, and at least two queue buffers which are arranged in the second data bus between the second processor or processor core and the second multiplexer inputs of the at least two multiplexers. The first processor or processor core is configured to have read access or write access only to one of the at least two interleaved memory banks within one clock cycle.

Abstract: A processor system comprises a memory having at least two interleaved memory banks, at least two multiplexers which are respectively coupled to one of the at least two interleaved memory banks via a respective memory bank bus, a first processor or processor core which is coupled to first multiplexer inputs of the at least two multiplexers via a first data bus, a second processor or processor core which is coupled to second multiplexer inputs of the at least two multiplexers via a second data bus, and at least two queue buffers which are arranged in the second data bus between the second processor or processor core and the second multiplexer inputs of the at least two multiplexers. The first processor or processor core is configured to have read access or write access only to one of the at least two interleaved memory banks within one clock cycle.

Abstract: A processor system includes an application processor, which has a processor core and hardware performance counters, and a monitoring processor, which is coupled to the application processor by a data transmission interface. The monitoring processor has a look-up table, in which target performance profiles of the progression over time of performance events of the hardware performance counters are stored for an application which is to be executed on the application processor and monitored. The monitoring processor has an evaluating logic which is linked to the look-up table and is configured to record the progression over time of performance events of the hardware performance counters during the execution of the application to be monitored on the application processor and to compare the progression with the target performance profiles stored in the look-up table.

Abstract: A processor system includes an application processor, which has a processor core and hardware performance counters, and a monitoring processor, which is coupled to the application processor by a data transmission interface. The monitoring processor has a look-up table, in which target performance profiles of the progression over time of performance events of the hardware performance counters are stored for an application which is to be executed on the application processor and monitored. The monitoring processor has an evaluating logic which is linked to the look-up table and is configured to record the progression over time of performance events of the hardware performance counters during the execution of the application to be monitored on the application processor and to compare the progression with the target performance profiles stored in the look-up table.

Abstract: The invention relates to a method for executing computer usable program code or a program made up of program parts on a multi-core processor (1) with a multiplicity of execution units (21, 22, 23, 24), each of which comprises a local memory (201) and at least one processing unit (202) communicatively linked to the local memory, wherein each of the execution units (21, 22, 23, 24) is connected to a communications network (30) for data exchange. One or more program parts are stored in at least some of the local memories (201) of the majority of execution units (21, 22, 23, 24). Execution of a program part is performed by the processing unit (202) of the particular execution unit (21, 22, 23, 24) that has the program part stored in its local memory (201).

Abstract: The present invention relates to a processor that, as its main feature, has an internal raster of ALUs, with the help of which sequential programs are executed. The connections between the ALUs are automatically created at runtime dynamically by means of multiplexers. A central decoding and configuration unit that creates configuration data for the ALU grid from a stream of conventional assembler commands at runtime is responsible for creating the connections. In addition to the ALU grid, a special unit for the execution of memory accesses and another unit for the processing of branch instructions are provided. The novel architecture that is the foundation of the processor makes efficient execution of both control flow- and data flow-oriented tasks possible.