Patents by Inventor Sasha Kweskin
Sasha Kweskin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10985049Abstract: A method is provided for preparing semiconductor structure, e.g., a semiconductor on insulator structure, comprising a device layer having a smooth surface. The method provided involves smoothing a semiconductor substrate surface by making use of stress enhanced surface diffusion at elevated temperatures. The purpose of this method is to reach atomic scale surface smoothness (for example, smoothness in the range of between 1.0 and 1.5 angstroms as measured according to root mean square over a 30 um×30 um AFM measurement), which is required in advanced (sub 28 nm) CMOS device fabrication.Type: GrantFiled: September 17, 2020Date of Patent: April 20, 2021Assignee: GlobalWafers Co., Ltd.Inventors: Gang Wang, Charles R. Lottes, Sasha Kweskin
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Publication number: 20200411364Abstract: A method is provided for preparing semiconductor structure, e.g., a semiconductor on insulator structure, comprising a device layer having a smooth surface. The method provided involves smoothing a semiconductor substrate surface by making use of stress enhanced surface diffusion at elevated temperatures. The purpose of this method is to reach atomic scale surface smoothness (for example, smoothness in the range of between 1.0 and 1.5 angstroms as measured according to root mean square over a 30 um×30 um AFM measurement), which is required in advanced (sub 28 nm) CMOS device fabrication.Type: ApplicationFiled: September 17, 2020Publication date: December 31, 2020Inventors: Gang Wang, Charles R. Lottes, Sasha Kweskin
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Patent number: 10818539Abstract: A method is provided for preparing semiconductor structure, e.g., a semiconductor on insulator structure, comprising a device layer having a smooth surface. The method provided involves smoothing a semiconductor substrate surface by making use of stress enhanced surface diffusion at elevated temperatures. The purpose of this method is to reach atomic scale surface smoothness (for example, smoothness in the range of between 1.0 and 1.5 angstroms as measured according to root mean square over a 30 um×30 um AFM measurement), which is required in advanced (sub 28 nm) CMOS device fabrication.Type: GrantFiled: August 29, 2019Date of Patent: October 27, 2020Assignee: GlobalWafers Co., Ltd.Inventors: Gang Wang, Charles R. Lottes, Sasha Kweskin
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Patent number: 10796946Abstract: A method is provided for preparing a semiconductor-on-insulator structure comprising a multilayer dielectric layer.Type: GrantFiled: October 7, 2019Date of Patent: October 6, 2020Assignee: SunEdison Semiconductor Limited (UEN201334164H)Inventors: Henry Frank Erk, Sasha Kweskin, Jeffrey L. Libbert, Mayank Bulsara
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Patent number: 10755966Abstract: A method is provided for preparing semiconductor structure, e.g., a semiconductor on insulator structure, comprising a device layer having a smooth surface. The method provided involves smoothing a semiconductor substrate surface by making use of stress enhanced surface diffusion at elevated temperatures. The purpose of this method is to reach atomic scale surface smoothness (for example, smoothness in the range of between 1.0 and 1.5 angstroms as measured according to root mean square over a 30 um×30 um AFM measurement), which is required in advanced (sub 28 nm) CMOS device fabrication.Type: GrantFiled: July 9, 2019Date of Patent: August 25, 2020Assignee: GlobaWafers Co., Ltd.Inventors: Gang Wang, Charles R. Lottes, Sasha Kweskin
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Publication number: 20200035544Abstract: A method is provided for preparing a semiconductor-on-insulator structure comprising a multilayer dielectric layer.Type: ApplicationFiled: October 7, 2019Publication date: January 30, 2020Inventors: Henry Frank Erk, Sasha Kweskin, Jeffrey L. Libbert, Mayank Bulsara
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Patent number: 10529616Abstract: A method is provided for preparing semiconductor structure, e.g., a semiconductor on insulator structure, comprising a device layer having a smooth surface. The method provided involves smoothing a semiconductor substrate surface by making use of stress enhanced surface diffusion at elevated temperatures. The purpose of this method is to reach atomic scale surface smoothness (for example, smoothness in the range of between 1.0 and 1.5 angstroms as measured according to root mean square over a 30 um×30 um AFM measurement), which is required in advanced (sub 28 nm) CMOS device fabrication.Type: GrantFiled: November 15, 2016Date of Patent: January 7, 2020Assignee: GlobalWafers Co., Ltd.Inventors: Gang Wang, Charles R. Lottes, Sasha Kweskin
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Publication number: 20190385901Abstract: A method is provided for preparing semiconductor structure, e.g., a semiconductor on insulator structure, comprising a device layer having a smooth surface. The method provided involves smoothing a semiconductor substrate surface by making use of stress enhanced surface diffusion at elevated temperatures. The purpose of this method is to reach atomic scale surface smoothness (for example, smoothness in the range of between 1.0 and 1.5 angstroms as measured according to root mean square over a 30 um×30 um AFM measurement), which is required in advanced (sub 28 nm) CMOS device fabrication.Type: ApplicationFiled: August 29, 2019Publication date: December 19, 2019Inventors: Gang Wang, Charles R. Lottes, Sasha Kweskin
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Patent number: 10475696Abstract: A method is provided for preparing a semiconductor-on-insulator structure comprising a multilayer dielectric layer.Type: GrantFiled: June 6, 2018Date of Patent: November 12, 2019Assignee: SunEdison Semiconductor Limited (UEN201334164H)Inventors: Henry Frank Erk, Sasha Kweskin, Jeffrey L. Libbert, Mayank Bulsara
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Publication number: 20190333804Abstract: A method is provided for preparing semiconductor structure, e.g., a semiconductor on insulator structure, comprising a device layer having a smooth surface. The method provided involves smoothing a semiconductor substrate surface by making use of stress enhanced surface diffusion at elevated temperatures. The purpose of this method is to reach atomic scale surface smoothness (for example, smoothness in the range of between 1.0 and 1.5 angstroms as measured according to root mean square over a 30 um×30 um AFM measurement), which is required in advanced (sub 28 nm) CMOS device fabrication.Type: ApplicationFiled: July 9, 2019Publication date: October 31, 2019Inventors: Gang Wang, Charles R. Lottes, Sasha Kweskin
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Publication number: 20190019721Abstract: A method is provided for preparing a semiconductor-on-insulator structure comprising a multilayer dielectric layer.Type: ApplicationFiled: June 6, 2018Publication date: January 17, 2019Inventors: Henry Frank Erk, Sasha Kweskin, Jeffrey L. Libbert, Mayank Bulsara
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Publication number: 20180330983Abstract: A method is provided for preparing semiconductor structure, e.g., a semiconductor on insulator structure, comprising a device layer having a smooth surface. The method provided involves smoothing a semiconductor substrate surface by making use of stress enhanced surface diffusion at elevated temperatures. The purpose of this method is to reach atomic scale surface smoothness (for example, smoothness in the range of between 1.0 and 1.5 angstroms as measured according to root mean square over a 30 um×30 um AFM measurement), which is required in advanced (sub 28 nm) CMOS device fabrication.Type: ApplicationFiled: November 15, 2016Publication date: November 15, 2018Inventors: Gang Wang, Charles R. Lottes, Sasha Kweskin
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Patent number: 8476142Abstract: Aspects of the disclosure pertain to methods of preferentially filling narrow trenches with silicon oxide while not completely filling wider trenches and/or open areas. In embodiments, dielectric layers are deposited by flowing a silicon-containing precursor and ozone into a processing chamber such that a relatively dense first portion of a silicon oxide layer followed by a more porous (and more rapidly etched) second portion of the silicon oxide layer. Narrow trenches are filled with dense material whereas open areas are covered with a layer of dense material and more porous material. Dielectric material in wider trenches may be removed at this point with a wet etch while the dense material in narrow trenches is retained.Type: GrantFiled: March 21, 2011Date of Patent: July 2, 2013Assignee: Applied Materials, Inc.Inventors: Sasha Kweskin, Hiroshi Hamana, Paul Edward Gee, Shankar Venkataraman, Kadar Sapre
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Patent number: 8236708Abstract: Aspects of the disclosure pertain to methods of depositing dielectric layers on patterned substrates. In embodiments, dielectric layers are deposited by flowing BIS(DIETHYLAMINO)SILANE (BDEAS), ozone and molecular oxygen into a processing chamber such that a relatively uniform dielectric growth rate is achieved across the patterned substrate surface. The deposition of dielectric layers grown according to embodiments may have a reduced dependence on pattern density while still being suitable for non-sacrificial applications.Type: GrantFiled: August 13, 2010Date of Patent: August 7, 2012Assignee: Applied Materials, Inc.Inventors: Sasha Kweskin, Paul Edward Gee, Shankar Venkataraman, Kedar Sapre
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Publication number: 20110250731Abstract: Aspects of the disclosure pertain to methods of preferentially filling narrow trenches with silicon oxide while not completely filling wider trenches and/or open areas. In embodiments, dielectric layers are deposited by flowing a silicon-containing precursor and ozone into a processing chamber such that a relatively dense first portion of a silicon oxide layer followed by a more porous (and more rapidly etched) second portion of the silicon oxide layer. Narrow trenches are filled with dense material whereas open areas are covered with a layer of dense material and more porous material. Dielectric material in wider trenches may be removed at this point with a wet etch while the dense material in narrow trenches is retained.Type: ApplicationFiled: March 21, 2011Publication date: October 13, 2011Applicant: Applied Materials, Inc.Inventors: Sasha Kweskin, Hiroshi Hamana, Paul Edward Gee, Shankar Venkataraman, Kadar Sapre
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Publication number: 20110223774Abstract: Aspects of the disclosure pertain to methods of depositing dielectric layers on patterned substrates. In embodiments, dielectric layers are deposited by flowing BIS(DIETHYLAMINO)SILANE (BDEAS), ozone and molecular oxygen into a processing chamber such that a relatively uniform dielectric growth rate is achieved across the patterned substrate surface. The deposition of dielectric layers grown according to embodiments may have a reduced dependence on pattern density while still being suitable for non-sacrificial applications.Type: ApplicationFiled: August 13, 2010Publication date: September 15, 2011Applicant: Applied Materials, Inc.Inventors: Sasha Kweskin, Paul Edward Gee, Shankar Venkataraman, Kedar Sapre
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Patent number: 7994019Abstract: Aspects of the disclosure pertain to methods of depositing conformal silicon oxide layers on patterned substrates. In embodiments, dielectric layers are deposited by flowing a silicon-containing precursor and ozone into a processing chamber such that a relatively uniform dielectric growth rate is achieved across the patterned substrate surface having heterogeneous materials and/or a heterogeneous pattern density distribution. The deposition of dielectric layers grown according to embodiments may have a reduced dependence on underlying material and pattern density while still being suitable for non-sacrificial applications. Reduction in dependence on pattern density is achieved by terminating deposition near the end of an incubation period. Multiple deposition cycles may be conducted in series since the beneficial nature of the incubation period may repeat after a pause in deposition.Type: GrantFiled: September 27, 2010Date of Patent: August 9, 2011Assignee: Applied Materials, Inc.Inventors: Sasha Kweskin, Paul Edward Gee, Shankar Venkataraman, Kedar Sapre