Patents by Inventor Sashank KRISHNAMURTHY
Sashank KRISHNAMURTHY has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12671384Abstract: A filter includes a plurality of filtering paths. The plurality of filtering paths is driven by a corresponding plurality of local oscillator (LO) signals associated with an LO frequency. Each of the LO signals has a phase of a plurality of phases. Each filtering path of the plurality of filtering paths includes a plurality of signal generation branches. The plurality of signal generation branches is configured to receive a harmonic LO signal based on a fraction of the LO frequency, and generate an LO signal of the corresponding plurality of LO signals associated with the LO frequency using the harmonic LO signal.Type: GrantFiled: December 27, 2022Date of Patent: June 30, 2026Assignee: Intel CorporationInventors: Run Levinger, Soumya Gupta, Sashank Krishnamurthy, Ashoke Ravi, Ofir Degani
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Publication number: 20260171974Abstract: A voltage-mode amplifier, comprising a first filter stage, comprising: a first voltage amplifier, connected to an input trace, and configured to amplify a signal conducted along the input trace; and a first N-path filter, connected to the input trace; wherein the first N-path filter is configured to shunt to a first reference voltage frequency from the signal; and a second filter stage, connected to the input trace in parallel to the first filter stage, comprising: a second voltage amplifier, connected to the input trace, and configured to amplify the signal conducted along the input trace; and a second N-path filter, connected to the input trace; and wherein the second N-path filter is configured to shunt to a second reference voltage frequency from the signal.Type: ApplicationFiled: December 13, 2024Publication date: June 18, 2026Inventors: Sashank KRISHNAMURTHY, Ashoke RAVI, Ofir DEGANI, Soumya GUPTA, Uri GROSGLIK
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Patent number: 12556220Abstract: A tunable bandpass low-noise amplifier (LNA). The LNA includes a plurality of N-path filters and a plurality of cascode amplifiers. The cascode amplifiers are configured to amplify an input signal. Each N-path filter is coupled to a different one of the plurality of cascode amplifiers. The plurality of N-path filters are driven by local oscillator (LO) signals having different frequencies, and output nodes of the plurality of cascode amplifiers are coupled in parallel. The frequencies of the LO signals may be symmetrically spaced around a desired frequency (fLO). Each N-path filter may be coupled to a source of the common-gate device of the coupled cascode amplifier. The LO signals may be generated by a digital-to-time converter (DTC)-based frequency synthesizer. The frequencies of the LO signals supplied to the N-path filters may be adjusted to tune the bandwidth of the bandpass LNA.Type: GrantFiled: August 12, 2022Date of Patent: February 17, 2026Assignee: Intel CorporationInventors: Sashank Krishnamurthy, Ofir Degani, Ashoke Ravi
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Publication number: 20250385701Abstract: Disclosed herein are devices, systems, and methods for applying a post-distortion scheme to recover a desired signal from a received signal. The device includes processing circuitry connected to storage, where the processing circuitry causes one or more antennas to simultaneously transmit a transmitted signal and receive a received signal, wherein the received signal comprises a desired signal to be recovered from the received signal. The processing circuitry also causes a gain block to amplify the received signal and a leaked portion of the transmitted signal into an amplified composite signal. The processing circuitry also determines a distortion of the gain block on the received signal based on the transmitted signal. The processing circuitry also applies to the amplified composite signal an inversion of the distortion to recover the desired signal from the received signal.Type: ApplicationFiled: June 14, 2024Publication date: December 18, 2025Inventors: Elan BANIN, Oren Ezra AVRAHAM, Ofir DEGANI, Sashank KRISHNAMURTHY, Ashoke RAVI
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Publication number: 20250310158Abstract: A receiver apparatus includes front-end circuitry, feedforward equalizer (FFE) circuitry, and digital signal processor (DSP). The front-end circuitry is configured to convert an input signal into a digital signal. The FFE circuitry is coupled to the front-end circuitry and includes a first FFE circuit configured to generate a first equalized signal based on a pre-cursor signal associated with the digital signal. The FFE circuitry also includes a second FFE circuit cascaded with the first FFE circuit. The second FFE circuit generates a second equalized signal based on a post-cursor signal associated with the digital signal. The DSP generates an output signal based on at least one of the first equalized signal and the second equalized signal.Type: ApplicationFiled: March 28, 2024Publication date: October 2, 2025Inventors: Sashank Krishnamurthy, Mozhgan Mansuri
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Publication number: 20250219596Abstract: Embodiments may comprise low noise amplifier (LNA) circuitry with a tunable wideband and high linearity. Embodiments may increase the linearity of the LNA circuitry and reduce noise. The LNA circuitry may comprise an inverter having a differential input coupled with the antenna, a first cascode circuitry coupled between a differential output of the inverter and a second cascode stage circuitry, wherein the second cascode stage circuitry comprises a first N-path filter circuitry coupled with a first set of outputs of clock circuitry having a clock frequency of an incoming signal minus a delta frequency and a second N-path filter circuitry coupled with a second set of outputs of clock circuitry having a clock frequency of an incoming signal plus a delta frequency. Combining the response of the two N-path filter circuitries at plus and minus delta frequency may achieve frequency selectivity and attenuate blockers.Type: ApplicationFiled: December 29, 2023Publication date: July 3, 2025Inventors: Ashoke Ravi, Sashank Krishnamurthy, Soumya Gupta, Oren Ezra Avraham, Ofir Degani
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Publication number: 20250112603Abstract: An amplifier structure may include a first amplifier substructure having a first amplifier and a first filter structure and provide a first high frequency output signal and a first low frequency output signal having a frequency lower than a frequency of the first high frequency output signal. It may include a second amplifier substructure having a second amplifier and a second filter structure and provide a second high frequency output signal and a second low frequency output signal having a frequency lower than the frequency of the second high frequency output signal. It may include a first combination node configured to receive the first high frequency output signal and the second low frequency output signal and to provide a first amplified signal, and a second combination node configured to receive the first low frequency output signal and the second high frequency output signal and to provide a second amplified signal.Type: ApplicationFiled: September 29, 2023Publication date: April 3, 2025Inventors: Ashoke RAVI, Ofir DEGANI, Sashank KRISHNAMURTHY, Soumya GUPTA
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Publication number: 20250105860Abstract: Embodiments may comprise N-path filter circuitry with tunable radio frequency selectivity and up to 80 decibels per decade roll-off. The N-path filter may comprise at least one input transistor, wherein the at least one input transistor comprises a channel and a gate. A first end of the channel is coupled with a receiver circuitry input, wherein a second end of the channel is coupled with a load. The gate of the at least one input transistor is coupled with a clock circuitry input. The load may comprise a fourth order, all-pole driving point impedance. The impedance may shunt the second end of the channel to a circuit ground or a low voltage circuit rail via the impedance. And the impedance may comprise a first active impedance circuit coupled in series with a second active impedance circuit.Type: ApplicationFiled: September 25, 2023Publication date: March 27, 2025Applicant: Intel CorporationInventor: Sashank Krishnamurthy
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Publication number: 20250097081Abstract: Embodiments herein relate to an equalizer in a communication system. In an example implementation, the communication system is an optical system including a Vertical-Cavity Surface-Emitting Laser (VCSEL). A transfer function of the equalizer has two complex-zeroes to compensate for a group delay variation due to an underdamped complex-pole pair of the VCSEL optical response. The equalizer may include a first transistor having a control gate coupled to an input path, a drain coupled to an output path, and a source, and first, second and third paths coupled between the source and ground. The first path includes, in series, a resistor, a node and a capacitor, the second path includes a second transistor having a control gate coupled to the node, and the third path includes a capacitor. A tuning process can be used to achieve a desired frequency and quality factor.Type: ApplicationFiled: September 14, 2023Publication date: March 20, 2025Inventors: Sashank Krishnamurthy, Mozhgan Mansuri
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Publication number: 20240213947Abstract: A filter includes a plurality of filtering paths. The plurality of filtering paths is driven by a corresponding plurality of local oscillator (LO) signals associated with an LO frequency. Each of the LO signals has a phase of a plurality of phases. Each filtering path of the plurality of filtering paths includes a plurality of signal generation branches. The plurality of signal generation branches is configured to receive a harmonic LO signal based on a fraction of the LO frequency, and generate an LO signal of the corresponding plurality of LO signals associated with the LO frequency using the harmonic LO signal.Type: ApplicationFiled: December 27, 2022Publication date: June 27, 2024Inventors: Run Levinger, SOUMYA GUPTA, SASHANK KRISHNAMURTHY, Ashoke Ravi, Ofir Degani
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Publication number: 20240056120Abstract: A tunable bandpass low-noise amplifier (LNA). The LNA includes a plurality of N-path filters and a plurality of cascode amplifiers. The cascode amplifiers are configured to amplify an input signal. Each N-path filter is coupled to a different one of the plurality of cascode amplifiers. The plurality of N-path filters are driven by local oscillator (LO) signals having different frequencies, and output nodes of the plurality of cascode amplifiers are coupled in parallel. The frequencies of the LO signals may be symmetrically spaced around a desired frequency (fLO). Each N-path filter may be coupled to a source of the common-gate device of the coupled cascode amplifier. The LO signals may be generated by a digital-to-time converter (DTC)-based frequency synthesizer. The frequencies of the LO signals supplied to the N-path filters may be adjusted to tune the bandwidth of the bandpass LNA.Type: ApplicationFiled: August 12, 2022Publication date: February 15, 2024Inventors: Sashank KRISHNAMURTHY, Ofir DEGANI, Ashoke RAVI