Patents by Inventor Sashi Balasingam

Sashi Balasingam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor inspection and metrology systems for distributing job among the CPUs or GPUs based on logical image processing boundaries
    Patent number: 11237872
    Abstract: Real-time job distribution software architectures for high bandwidth, hybrid processor computation systems for semiconductor inspection and metrology are disclosed. The imaging processing computer architecture can be scalable by changing the number of CPUs and GPUs to meet computing needs. The architecture is defined using a master node and one or more worker nodes to run image processing jobs in parallel for maximum throughput. The master node can receive input image data from a semiconductor wafer or reticle. Jobs based on the input image data are distributed to one of the worker nodes. Each worker node can include at least one CPU and at least one GPU. The image processing job can contain multiple tasks, and each of the tasks can be assigned to one of the CPU or GPU in the worker node using a worker job manager to process the image.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: February 1, 2022
    Assignee: KLA-TENCOR CORPORATION
    Inventors: Ajay Gupta, Sankar Venkataraman, Sashi Balasingam, Mohan Mahadevan
  • Scalable and Flexible Job Distribution Architecture for a Hybrid Processor System to Serve High Bandwidth Real Time Computational Systems Used in Semiconductor Inspection and Metrology Systems
    Publication number: 20180341525
    Abstract: Real-time job distribution software architectures for high bandwidth, hybrid processor computation systems for semiconductor inspection and metrology are disclosed. The imaging processing computer architecture can be scalable by changing the number of CPUs and GPUs to meet computing needs. The architecture is defined using a master node and one or more worker nodes to run image processing jobs in parallel for maximum throughput. The master node can receive input image data from a semiconductor wafer or reticle. Jobs based on the input image data are distributed to one of the worker nodes. Each worker node can include at least one CPU and at least one GPU. The image processing job can contain multiple tasks, and each of the tasks can be assigned to one of the CPU or GPU in the worker node using a worker job manager to process the image.
    Type: Application
    Filed: May 14, 2018
    Publication date: November 29, 2018
    Inventors: Ajay Gupta, Sankar Venkataraman, Sashi Balasingam, Mohan Mahadevan