Abstract: An apparatus for enabling duty cycle locking at the rising/falling edge of the clock includes a counter that receives a gated input clock. A lock detector receives an input clock for generating control signals. An address decoder is connected to the counter for generating a set of selection signals. A first multiplexer includes select lines connected to receive the selection signals. A plurality of delay chains provide multiple output taps with a first delay chain connected to the first multiplexer. A second multiplexer is connected to one of the plurality of delay chains with its select lines being hard wired. A latch is connected to the output of the first multiplexer and the second multiplexer for providing the output.