Patents by Inventor Sashi S. KANDANUR
Sashi S. KANDANUR has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240071883Abstract: Embodiments disclosed herein include cores for package substrates. In an embodiment, the core comprises a first substrate, where the first substrate comprises glass. In an embodiment, the core further comprises a first through glass via (TGV) through the first substrate and a second substrate, where the second substrate comprises glass. In an embodiment, the core further comprises a second TGV through the second substrate, where the first TGV is aligned with the second TGV.Type: ApplicationFiled: August 23, 2022Publication date: February 29, 2024Inventors: Brandon C. MARIN, Sashi S. KANDANUR, Suddhasattwa NAD, Srinivas V. PIETAMBARAM, Gang DUAN, Jeremy D. ECTON
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Publication number: 20230107096Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to glass layers within a package that include one or more high aspect ratio TGV that are filled with conductive material. The TGV extends from a first side of the glass layer to a second side of the glass layer opposite the first side and are filled with conductive material to provide a high-quality electrical connection between the first side of the glass layer and the second side of the glass layer, where a portion of the wall of the TGV includes titanium. Other embodiments may be described and/or claimed.Type: ApplicationFiled: September 21, 2021Publication date: April 6, 2023Inventors: Darko GRUJICIC, Sashi S. KANDANUR, Helme A. CASTRO DE LA TORRE, Srinivas V. PIETAMBARAM, Marcel WALL, Suddhasattwa NAD, Rengarajan SHANMUGAM, Benjamin DUONG
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Publication number: 20230095846Abstract: Glass substrates having transverse capacitors for use with semiconductor packages and related methods are disclosed. An example semiconductor package includes a glass substrate having a through glass via between a first surface and a second surface opposite the first surface. A transverse capacitor is located in the through glass via. The transverse capacitor includes a dielectric material positioned in a first portion of the through glass via, a first barrier/seed layer positioned in a second portion of the through glass via, and a first conductive material positioned in a third portion of the through glass via.Type: ApplicationFiled: September 24, 2021Publication date: March 30, 2023Inventors: Benjamin T. Duong, Srinivas V. Pietambaram, Aleksandar Aleksov, Helme Castro De La Torre, Kristof Darmawikarta, Darko Grujicic, Sashi S. Kandanur, Suddhasattwa Nad, Rengarajan Shanmugam, Thomas I. Sounart, Marcel A. Wall
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Publication number: 20230091666Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques directed to embedding capacitors in through glass vias within a glass core of a substrate. In embodiments, the through glass vias may extend entirely from a first side of the glass core to a second side of the glass core opposite the first side. Layers of electrically conductive material and dielectric material may then be deposited within the through glass via to form a capacitor. the capacitor may then be electrically coupled with electrical routings on buildup layers on either side of the glass core. Other embodiments may be described and/or claimed.Type: ApplicationFiled: September 22, 2021Publication date: March 23, 2023Inventors: Benjamin DUONG, Aleksandar ALEKSOV, Helme A. CASTRO DE LA TORRE, Kristof DARMAWIKARTA, Darko GRUJICIC, Sashi S. KANDANUR, Suddhasattwa NAD, Srinivas V. PIETAMBARAM, Rengarajan SHANMUGAM, Thomas L. SOUNART, Marcel WALL
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Publication number: 20230082385Abstract: An electronic device comprises an electronic package with a glass core. The glass core includes a first surface and a second surface opposite the first surface, at least one through-glass via (TGV) extending through the glass core from the first surface to the second surface, and including an electrically conductive material, and wherein the at least one TGV includes a first portion having a first width and a second portion having a second width different from the first width.Type: ApplicationFiled: September 14, 2021Publication date: March 16, 2023Inventors: Jeremy D. Ecton, Kristof Darmawikarta, Sashi S. Kandanur, Srinivas Venkata Ramanuja Pietambaram, Darko Grujicic, Marcel Arlan Wall, Suddhasattwa Nad, Benjamin Duong, Rengarajan Shanmugam, Bai Nie, Helme Castro De La Torre
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Patent number: 11127682Abstract: Semiconductor packages having nonspherical filler particles are described. In an embodiment, a semiconductor package includes a package substrate having a dielectric layer over an electrical interconnect. The dielectric layer includes nonspherical filler particles in a resin matrix. The nonspherical filler particles have an aspect ratio greater than one.Type: GrantFiled: June 30, 2017Date of Patent: September 21, 2021Assignee: Intel CorporationInventors: Sashi S. Kandanur, David Allen Unruh, Jr., Srinivas V. Pietambaram
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Patent number: 10856424Abstract: A method that includes electroplating both sides of a core and the through hole of a core with a conductive material to cover both sides of the core with the conductive material and to form a conductive bridge in the through hole, wherein the core has a thickness greater than 200 microns; etching the conductive material that covers both sides of the core to reduce the thickness of the conductive material to about 1 micron; applying a film resist to the core; exposing and developing the resist film to form patterns on the conductive material on both sides of the core; and electroplating additional conductive material on the (i) conductive material on both sides of the core (ii) conductive material within the through hole; and (iii) conductive bridge to fill the through hole with conductive material without any voids and to form conductive patterns on both sides of the core.Type: GrantFiled: September 25, 2015Date of Patent: December 1, 2020Assignee: Intel CorporationInventors: Sri Ranga Sai Boyapati, Amanda E. Schuckman, Sashi S. Kandanur, Srinivas Pietambaram, Mark Hlad, Kristof Darmawikarta
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Patent number: 10798817Abstract: Apparatus and methods are provided for flexible and stretchable circuits. In an example, a method can include forming a first flexible conductor on a substrate, the first flexible conductor including a first conductive trace surrounded on three sides by a first dielectric, and forming a second flexible conductor on top of the first flexible conductor, the first flexible conductor located between the second flexible conductor and the substrate, the second flexible conductor including a second conductive trace surrounded by a second dielectric.Type: GrantFiled: December 11, 2015Date of Patent: October 6, 2020Assignee: Intel CorporationInventors: Aleksandar Aleksov, Javier Soto Gonzalez, Meizi Jiao, Shruti R. Jaywant, Oscar Ojeda, Sashi S. Kandanur, Srinivas Venkata Ramanuja Pietambaram, Roy Dittler, Rajat Goyal, Dilan Seneviratne
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Patent number: 10428439Abstract: A method including running a simulated plating process on a substrate using a base shield, the base shield including a plurality of openings therethrough defining an array including two coordinates; after running the simulated plating process, determining if a predetermined criterion for the simulated plating process is satisfied; and if the predetermined criterion is not satisfied, adjusting one or more of the plurality of openings. A machine readable medium including program instructions that when executed by a controller cause the controller to perform a method including running a simulated plating process on a substrate using a base shield, the base shield including a plurality of openings therethrough defining an array including two coordinates; after running the simulated plating process, determining if a predetermined criterion for the simulated plating process is satisfied; and if the predetermined criterion is not satisfied, adjusting one or more of the plurality of openings.Type: GrantFiled: November 16, 2015Date of Patent: October 1, 2019Assignee: Intel CorporationInventors: Nicholas S. Haehn, Sashi S. Kandanur
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Patent number: 10327330Abstract: Some forms relate to an example stretchable electronic assembly. The stretchable electronic assembly includes a stretchable body that includes electronic components. A plurality of meandering conductors electrically connect the electronic components. The plurality of meandering conductors may be exposed from the stretchable body. A plurality of conductive pads are electrically connected to at least one of the electronic components or some of the plurality of meandering conductors. The plurality of conductive pads may be exposed from the stretchable body. The stretchable body includes an upper surface and lower surface. The plurality of meandering conductors may be exposed from the lower surface (in addition to, or alternatively to, the upper surface) of the stretchable body.Type: GrantFiled: September 24, 2015Date of Patent: June 18, 2019Assignee: Intel CorporationInventors: Aleksandar Aleksov, Adel A. Elsherbini, Javier Soto Gonzalez, Dilan Seneviratne, Shruti R. Jaywant, Sashi S. Kandanur, Srinivas Pietambaram, Nadine L. Dabby, Braxton Lathrop, Rajat Goyal, Vivek Raghunathan
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Publication number: 20180376585Abstract: Apparatus and methods are provided for flexible and stretchable circuits. In an example, a method can include forming a first flexible conductor on a substrate, the first flexible conductor including a first conductive trace surrounded on three sides by a first dielectric, and forming a second flexible conductor on top of the first flexible conductor, the first flexible conductor located between the second flexible conductor and the substrate, the second flexible conductor including a second conductive trace surrounded by a second dielectric.Type: ApplicationFiled: December 11, 2015Publication date: December 27, 2018Inventors: Aleksandar Aleksov, Javier Soto Gonzalea, Meizi Jiao, Shruti R. Jaywant, Oscar Ojeda, Sashi S. Kandanur, Srinivas Pietambaram, Roy Dittler, Rajat Goyal, Dilan Seneviratne
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Publication number: 20180295720Abstract: Some forms relate to an example stretchable electronic assembly. The stretchable electronic assembly includes a stretchable body that includes electronic components. A plurality of meandering conductors electrically connect the electronic components. The plurality of meandering conductors may be exposed from the stretchable body. A plurality of conductive pads are electrically connected to at least one of the electronic components or some of the plurality of meandering conductors. The plurality of conductive pads may be exposed from the stretchable body. The stretchable body includes an upper surface and lower surface. The plurality of meandering conductors may be exposed from the lower surface (in addition to, or alternatively to, the upper surface) of the stretchable body.Type: ApplicationFiled: September 24, 2015Publication date: October 11, 2018Inventors: Aleksandar Aleksov, Adel A. Elsherbini, Javier Soto Gonzalez, Dilan Seneviratne, Shruti R. Jaywant, Sashi S. Kandanur, Srinivas Pietambaram, Nadine L. Dabby, Braxton Lathrop, Rajat Goyal, Vivek Raghunathan
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Publication number: 20180288885Abstract: A method that includes electroplating both sides of a core and the through hole of a core with a conductive material to cover both sides of the core with the conductive material and to form a conductive bridge in the through hole, wherein the core has a thickness greater than 200 microns; etching the conductive material that covers both sides of the core to reduce the thickness of the conductive material to about 1 micron; applying a film resist to the core; exposing and developing the resist film to form patterns on the conductive material on both sides of the core; and electroplating additional conductive material on the (i) conductive material on both sides of the core (ii) conductive material within the through hole; and (iii) conductive bridge to fill the through hole with conductive material without any voids and to form conductive patterns on both sides of the core.Type: ApplicationFiled: September 25, 2015Publication date: October 4, 2018Inventors: Sri Ranga Sai Boyapati, Amanda E. Schuckman, Sashi S. Kandanur, Srinivas Pietambaram, Mark Hlad, Kristof Darmawikarta
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Publication number: 20170140076Abstract: A method including running a simulated plating process on a substrate using a base shield, the base shield including a plurality of openings therethrough defining an array including two coordinates; after running the simulated plating process, determining if a predetermined criterion for the simulated plating process is satisfied; and if the predetermined criterion is not satisfied, adjusting one or more of the plurality of openings. A machine readable medium including program instructions that when executed by a controller cause the controller to perform a method including running a simulated plating process on a substrate using a base shield, the base shield including a plurality of openings therethrough defining an array including two coordinates; after running the simulated plating process, determining if a predetermined criterion for the simulated plating process is satisfied; and if the predetermined criterion is not satisfied, adjusting one or more of the plurality of openings.Type: ApplicationFiled: November 16, 2015Publication date: May 18, 2017Inventors: Nicholas S. HAEHN, Sashi S. KANDANUR