Patents by Inventor Sasikala J

Sasikala J has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Capacitive Compensation for Vertical Interconnect Accesses
    Publication number: 20220201857
    Abstract: Multiple designs for a multi-layer circuit may be simulated to determine impedance profiles of each design, allowing a circuit designer to select a design based on the impedance profiles. One feature that can be modified is the structure surrounding the barrels of a differential VIA on layers that are not connected to the differential VIA. Specifically, one antipad can be used that surrounds both barrels or two antipads can be used, with one antipad for each barrel. Additionally, the size of the antipad or antipads can be modified. These modifications affect the impedance of the differential VIA. Additionally, a conductive region may be placed that connects to the VIA barrel even though the circuit on the layer does not connect to the VIA. This unused pad, surrounded by a non-conductive region, also affects the impedance of the differential VIA.
    Type: Application
    Filed: March 9, 2022
    Publication date: June 23, 2022
    Inventors: Hansel Desmond Dsilva, Sasikala J, Abhishek Jain, Amit Kumar
  • Capacitive compensation for vertical interconnect accesses
    Patent number: 11324119
    Abstract: Multiple designs for a multi-layer circuit may be simulated to determine impedance profiles of each design, allowing a circuit designer to select a design based on the impedance profiles. One feature that can be modified is the structure surrounding the barrels of a differential VIA on layers that are not connected to the differential VIA. Specifically, one antipad can be used that surrounds both barrels or two antipads can be used, with one antipad for each barrel. Additionally, the size of the antipad or antipads can be modified. These modifications affect the impedance of the differential VIA. Additionally, a conductive region may be placed that connects to the VIA barrel even though the circuit on the layer does not connect to the VIA. This unused pad, surrounded by a non-conductive region, also affects the impedance of the differential VIA.
    Type: Grant
    Filed: October 23, 2020
    Date of Patent: May 3, 2022
    Assignee: Achronix Semiconductor Corporation
    Inventors: Hansel Desmond Dsilva, Sasikala J, Abhishek Jain, Amit Kumar
  • Capacitive Compensation for Vertical Interconnect Accesses
    Publication number: 20220132663
    Abstract: Multiple designs for a multi-layer circuit may be simulated to determine impedance profiles of each design, allowing a circuit designer to select a design based on the impedance profiles. One feature that can be modified is the structure surrounding the barrels of a differential VIA on layers that are not connected to the differential VIA. Specifically, one antipad can be used that surrounds both barrels or two antipads can be used, with one antipad for each barrel. Additionally, the size of the antipad or antipads can be modified. These modifications affect the impedance of the differential VIA. Additionally, a conductive region may be placed that connects to the VIA barrel even though the circuit on the layer does not connect to the VIA. This unused pad, surrounded by a non-conductive region, also affects the impedance of the differential VIA.
    Type: Application
    Filed: October 23, 2020
    Publication date: April 28, 2022
    Inventors: Hansel Desmond Dsilva, Sasikala J, Abhishek Jain, Amit Kumar