Abstract: A spin orbit torque (SOT) memory device includes a SOT electrode having a spin orbit coupling material. The SOT electrode has a first sidewall and a second sidewall opposite to the first sidewall. The SOT memory device further includes a magnetic tunnel junction device on a portion of the SOT electrode. A first MTJ sidewall intersects the first SOT sidewall and a portion of the first MTJ sidewall and the SOT sidewall has a continuous first slope. The MTJ device has a second sidewall that does not extend beyond the second SOT sidewall and at least a portion of the second MTJ sidewall has a second slope.

Abstract: Approaches for integrating FE memory arrays into a processor, and the resulting structures are described. Simultaneous integrations of regions with ferroelectric (FE) cells and regions with standard interconnects are also described. FE cells include FE capacitors that include a FE stack of layers, which is encapsulated with a protection material. The protection material protects the FE stack of layers as structures for regular logic are fabricated in the same die.

Abstract: A multilayer free magnetic layer structure for spin-based magnetic memory is provided herein. The multilayer free magnetic structure is employed in a magnetic tunnel junction (MTJ) and includes antiferromagnetically coupled magnetic layers. In some cases, the antiferromagnetic coupling is mediated by RKKY interaction with a Ru, Ir, Mo, Cu, or Rh spacer layer. In some cases, low damping magnetic materials, such as CoFeB, FeB, or CoFeBMo are used for the antiferromagnetically coupled magnetic layers. By employing the multilayer free magnetic structure for the MTJ as variously described herein, the critical or switching current can be significantly reduced compared to, for example, an MTJ employing a single-layer free magnetic layer. Thus, higher device efficiencies can be achieved. In some cases, the magnetic layers of the multilayer free magnetic structure are perpendicular magnets, which can be employed, for example, in perpendicular spin-orbit torque (pSOT) memory devices.

Abstract: Ferroelectric capacitor is formed by conformably depositing a non-conductive dielectric over the etched first and second electrodes, and forming a metal cap or helmet over a selective part of the non-conductive dielectric, wherein the metal cap conforms to portions of sidewalls of the non-conductive dielectric. The metal cap is formed by applying physical vapor deposition at a grazing angle to selectively deposit a metal mask over the selective part of the non-conductive dielectric. The metal cap can also be formed by applying ion implantation with tuned etch rate. The method further includes isotopically etching the metal cap and the non-conductive dielectric such that non-conductive dielectric remains on sidewalls of the first and second electrodes but not on the third and fourth electrodes.

Abstract: A high-density low voltage ferroelectric (or paraelectric) memory bit-cell that includes a planar ferroelectric or paraelectric capacitor. The memory bit-cell comprises 1T1C configuration, where a plate-line is parallel to a word-line, or the plate-line is parallel to a bit-line. The memory bit-cell can be 1TnC, where ‘n’ is a number. In a 1TnC bit-cell, the capacitors are vertically stacked allowing for multiple values to be stored in a single bit-cell. The memory bit-cell can be multi-element FE gain bit-cell. In a multi-element FE gain bit-cell, data sensing is done with signal amplified by a gain transistor in the bit-cell. As such, higher storage density is realized using multi-element FE gain bit-cells. In some examples, the 1T1C, 1TnC, and multi-element FE gain bit-cells are multi-level bit-cells. To realize multi-level bit-cells, the capacitor is placed in a partially switched polarization state by applying different voltage levels or different time pulse widths at the same voltage level.

Abstract: The present disclosure is directed to systems and methods of implementing a neural network using in-memory, bit-serial, mathematical operations performed by a pipelined SRAM architecture (bit-serial PISA) circuitry disposed in on-chip processor memory circuitry. The on-chip processor memory circuitry may include processor last level cache (LLC) circuitry. The bit-serial PISA circuitry is coupled to PISA memory circuitry via a relatively high-bandwidth connection to beneficially facilitate the storage and retrieval of layer weights by the bit-serial PISA circuitry during execution. Direct memory access (DMA) circuitry transfers the neural network model and input data from system memory to the bit-serial PISA memory and also transfers output data from the PISA memory circuitry to system memory circuitry.

Abstract: The disclosed technology generally relates to ferroelectric materials and semiconductor devices, and more particularly to semiconductor memory devices incorporating doped polar materials. In one aspect, a semiconductor device comprises a capacitor which in turn comprises a polar layer comprising a base polar material doped with a dopant. The base polar material includes one or more metal elements and one or both of oxygen or nitrogen. The dopant comprises a metal element that is different from the one or more metal elements and is present at a concentration such that a ferroelectric switching voltage of the capacitor is different from that of the capacitor having the base polar material without being doped with the dopant by more than about 100 mV. The capacitor stack additionally comprises first and second crystalline conductive oxide electrodes on opposing sides of the polar layer.

Abstract: A new class of logic gates are presented that use non-linear polar material. The logic gates include multi-input majority gates. Input signals in the form of digital signals are driven to non-linear input capacitors on their respective first terminals. The second terminals of the non-linear input capacitors are coupled a summing node which provides a majority function of the inputs. In the multi-input majority or minority gates, the non-linear charge response from the non-linear input capacitors results in output voltages close to or at rail-to-rail voltage levels. In some examples, the nodes of the non-linear input capacitors are conditioned once in a while to preserve function of the multi-input majority gates.

Abstract: Embodiments herein relate to magnetically doping a spin orbit torque electrode (SOT) in a magnetic random access memory apparatus. In particular, the apparatus may include a free layer of a magnetic tunnel junction (MTJ) coupled to a SOT electrode that is magnetically doped to apply an effective magnetic field on the free layer, where the free layer has a magnetic polarization in a first direction and where current flowing through the magnetically doped SOT electrode is to cause the magnetic polarization of the free layer to change to a second direction that is substantially opposite to the first direction.

Abstract: An apparatus is provided which comprises: a magnetic junction (e.g., a magnetic tunneling junction or spin valve). The apparatus further includes a structure (e.g., an interconnect) comprising spin orbit material, the structure adjacent to the magnetic junction; first and second transistors. The first transistor is coupled to a bit-line and a first word-line, wherein the first transistor is adjacent to the magnetic junction. The second transistor is coupled to a first select-line and a second word-line, wherein the second transistor is adjacent to the structure, wherein the interconnect is coupled to a second select-line, and wherein the magnetic junction is between the first and second transistors.

Abstract: Techniques are provided for implementing a recurrent neuron (RN) using magneto-electric spin orbit (MESO) logic. An RN implementing the techniques according to an embodiment includes a first MESO device to apply a threshold function to an input signal provided at a magnetization port of the MESO device, and scale the result by a first weighting factor supplied at an input port of the MESO device to generate an RN output signal. The RN further includes a second MESO device to receive the RN output signal at a magnetization port of the second MESO device and generate a scaled previous RN state value. The scaled previous state value is a scaled and time delayed version of the RN output signal based on a second weighting factor. The RN input signal is a summation of the scaled previous state value of the RN with weighted synaptic input signals provided to the RN.

Abstract: An apparatus is provided which comprises a full adder including magnetoelectric material and spin orbit material. In some embodiments, the adder includes: a 3-bit carry generation structure and a multi-bit sum generation structure coupled to the 3-bit carry generation structure. In some embodiments, the 3-bit carry generation structure includes at least three cells comprising magnetoelectric material and spin orbit material, wherein the 3-bit carry generation structure is to perform a minority logic operation on first, second, and third inputs to generate a carry output. In some embodiments, the multi-bit sum generation structure includes at least four cells comprising magnetoelectric material and spin orbit material, wherein the multi-bit sum generation structure is to perform a minority logic operation on the first, second, and third inputs and the carry output to generate a sum output.

Abstract: Electrical devices with an integral thermoelectric generator comprising a spin-Seebeck insulator and a spin orbit coupling material, and associated methods of fabrication. A spin-Seebeck thermoelectric material stack may be integrated into macroscale power cabling as well as nanoscale device structures. The resulting structures are to leverage the spin-Seebeck effect (SSE), in which magnons may transport heat from a source (an active device or passive interconnect) and through the spin-Seebeck insulator, which develops a resulting spin voltage. The SOC material is to further convert the spin voltage into an electric voltage to complete the thermoelectric generation process. The resulting electric voltage may then be coupled into an electric circuit.

Abstract: The disclosed technology generally relates to ferroelectric materials and semiconductor devices, and more particularly to semiconductor memory devices incorporating doped polar materials. In one aspect, a semiconductor device comprises a capacitor which in turn comprises a polar layer comprising a base polar material doped with a dopant. The base polar material includes one or more metal elements and one or both of oxygen or nitrogen. The dopant comprises a metal element that is different from the one or more metal elements and is present at a concentration such that a ferroelectric switching voltage of the capacitor is different from that of the capacitor having the base polar material without being doped with the dopant by more than about 100 mV. The capacitor stack additionally comprises first and second crystalline conductive oxide electrodes on opposing sides of the polar layer.

Abstract: A memory device comprises a substrate having a front side and a backside, wherein a first conductive line is on the backside and a second conductive line is on the front side. A transistor is on the front side between the second conductive line and the substrate. A magnetic tunnel junction (MTJ) is on the backside between the first conductive line and the substrate, wherein one end of the MTJ is coupled through the substrate to the transistor and an opposite end of the MTJ is connected to the first conductive line, and wherein the transistor is further connected to the second conductive line on the front side.

Abstract: An apparatus is provided which comprises: a first stack comprising a magnetic insulating material (MI such as, EuS, EuO, YIG, TmIG, or GaMnAs) and a transition metal dichalcogenide (TMD such as MoS2, MoSe2, WS2, WSe2, PtS2, PtSe2, WTe2, MoTe2, or graphene; a second stack comprising an MI material and a TMD, wherein the first and second stacks are separated by an insulating material (e.g., oxide); a magnet (e.g., a ferromagnet or a paramagnet) adjacent to the TMDs of the first and second stacks, and also adjacent to the insulating material; and a magnetoelectric material (e.g., (LaBi)FeO3, LuFeO3, PMN-PT, PZT, AlN, or (SmBi)FeO3) adjacent to the magnet.

Abstract: The disclosed technology generally relates to ferroelectric materials and semiconductor devices, and more particularly to semiconductor memory devices incorporating doped polar materials. In one aspect, a semiconductor device comprises a transistor formed on a silicon substrate and a capacitor electrically connected to the transistor by a conductive via. The capacitor comprises upper and lower conductive oxide electrodes on opposing sides of a polar layer, wherein the lower conductive oxide electrode is electrically connected to a drain of the transistor.

Abstract: A new class of logic gates are presented that use non-linear polar material. The logic gates include multi-input majority gates. Input signals in the form of digital signals are driven to non-linear input capacitors on their respective first terminals. The second terminals of the non-linear input capacitors are coupled a summing node which provides a majority function of the inputs. The majority node is then coupled driver circuitry which can be any suitable logic gate such as a buffer, inverter, NAND gate, NOR gate, etc. In the multi-input majority or minority gates, the non-linear charge response from the non-linear input capacitors results in output voltages close to or at rail-to-rail voltage levels. Bringing the majority output close to rail-to-rail voltage eliminates the high leakage problem faced from majority gates formed using linear input capacitors.

Abstract: An apparatus is provided which comprises: a stack comprising a magnetic insulating material (MI such as EuS, EuO, YIG, TmIG, or GaMnAs) and a transition metal dichalcogenide (TMD such as MoS2, MoSe2, WS2, WSe2, PtS2, PtSe2, WTe2, MoTe2, or graphene), wherein the magnetic insulating material has a first magnetization; a magnet with a second magnetization, wherein the magnet is adjacent to the TMD of the stack; and an interconnect comprising a spin orbit material, wherein the interconnect is adjacent to the magnet.

Abstract: An apparatus is provided which comprises one or more magnetoelectric spin orbit (MESO) minority gates with different peripheral complementary metal oxide semiconductor (CMOS) circuit techniques in the device layer including: (1) current mirroring, (2) complementary supply voltages, (3) asymmetrical transistor sizing, and (4) using transmission gates. These MESO minority gates use the multi-phase clock to prevent back propagation of current so that MESO gate can correctly process the input data.