Abstract: A fully wearable, wireless soft electronic system that offers a portable, highly sensitive tracking of eye movements (vergence) via the combination of skin-conformal sensors and a virtual reality system. Advancement of material processing and printing technologies based on aerosol jet printing enables reliable manufacturing of skin-like sensors, while the flexible hybrid circuit based on elastomer and chip integration allows comfortable integration with a user's head. Analytical and computational study of a data classification algorithm provides a highly accurate tool for real-time detection and classification of ocular motions. In vivo demonstration with 14 human subjects captures the potential of the wearable electronics as a portable therapy system, whose minimized form factor facilitates seamless interplay with traditional wearable hardware.

Abstract: Methods and systems for tracking ocular vergence movements of an eye of a person are described. The methods and systems involve placement of flexible/stretchable skin-like electrodes on a person's head and recording the biopotential or electrooculogram of the person as the eye or eyes move to different focal positions, such as near distances, intermediate distances, and far distances. A data acquisition unit can record the electrooculogram and transmit the electrooculogram data to a computer for classification or for further processing. The data can be used with ophthalmic devices to provide a visual change for a person with the ophthalmic device.

Abstract: Aspects of the disclosure provide an integrated circuit (IC) chip having a memory controller. The memory controller includes a memory interface circuit configured to interface the IC chip with a memory chip having a memory array, and a first control circuit. The memory chip has a configuration circuit for adjusting one or more configurations of the memory chip. The first control circuit is configured to control the memory interface circuit and to communicate with the configuration circuit in the memory chip via the memory interface circuit to adjust the one or more configurations of the memory chip.

Abstract: The present disclosure describes methods and apparatus for implementing a signature-based sleep recovery operation flow for booting a system-on-chip (SoC). When the SoC begins its normal boot flow, a controller retrieves a sleep recovery signature from a register and compares the retrieved sleep recovery signature to a default signature. If the sleep recovery signature matches the default signature, the SoC enters a ROM checksum fail debug flow and, upon satisfying the requirements of the ROM checksum fail debug flow, enters a sleep recovery boot flow, which restores the SoC to the operational state it was in prior to entering the sleep mode. If the sleep recovery signature does not match the default signature, the SoC continues with the normal boot flow or, by use of external pins, can be forced into a normal debug mode flow so that the boot code can be debugged.

Abstract: Systems, methods, and other embodiments associated with providing real time closed loop control of memory access are described. According to one embodiment, a method includes accessing a memory of a computing device during real time operation of the computing device and detecting bit errors associated with the accessing of the memory. The method also includes generating a performance metric based on, at least in part, the detected bit errors during the real time operation of the computing device. The method further includes adjusting a setting of at least one timing element, of a plurality of timing elements of a physical layer of the computing device, based on the performance metric during the real time operation of the computing device to maintain a determined memory access performance.

Abstract: Aspects of the disclosure provide an integrated circuit (IC) chip having a memory controller. The memory controller includes a memory interface circuit configured to interface the IC chip with a memory chip having a memory array, and a first control circuit. The memory chip has a configuration circuit for adjusting one or more configurations of the memory chip. The first control circuit is configured to control the memory interface circuit and to communicate with the configuration circuit in the memory chip via the memory interface circuit to adjust the one or more configurations of the memory chip.

Abstract: Systems, methods, and other embodiments associated with providing dynamic switching between memory access modes are described. According to one embodiment, an apparatus includes first memory and second memory. The apparatus also includes a memory control logic configured to facilitate memory access of the first memory and the second memory using either a first memory access mode or a second memory access mode. The first memory access mode is configured to facilitate memory access of both the first memory and the second memory. The second memory access mode is configured to facilitate memory access of one of the first memory or the second memory. The memory control logic is configured to dynamically switch between the first memory access mode and the second memory access mode, without having to remap memory or reboot the system, in accordance with a region-based memory address mapping technique.