Patents by Inventor Saswati Das

Saswati Das has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12236138
    Abstract: Systems, methods, non-transitory computer-readable media for creating isolation between multiple domains. One system includes a VD level disperser configured to segregate new write commands based on virtual device (VD) identifiers and maintain separate VD specific in-place linked lists. The system further includes a Quality of Service (QOS) level disperser configured to segregate VD specific commands of the VD specific in-place linked lists based on each of the VD specific commands respective QoS domain identifiers and maintain separate QoS domain specific linked lists. The system further includes a superblock level disperser configured to segregate QoS domain specific commands of the QoS domain specific in-place linked lists based on each of the QoS domain specific commands respective superblock or placement identifiers, maintain separate superblock-specific in-place linked lists for each superblock or placement identifier, and provide the superblock-specific in-place linked lists to a write divider.
    Type: Grant
    Filed: April 3, 2023
    Date of Patent: February 25, 2025
    Assignee: KIOXIA CORPORATION
    Inventor: Saswati Das
  • Patent number: 12223187
    Abstract: The present invention is directed to an SSD that stores data in a plurality of regions of the SSD, each of the regions associated with a plurality of logical cluster addresses. The SSD also sets a deallocation status of each of the plurality of regions in a deallocate flag bitmap and sets a deallocation status of one or more sections of the deallocate flag bitmap in a deallocate summary table, wherein each of the one or more sections corresponds to more than one of the plurality of regions. In response to a shutdown or loss of power event, The SSD writes to non-volatile memory only sections of the deallocation flag bitmap with a predetermined deallocation status in the deallocate summary table. The SSD stores the deallocate flag bitmap is stored in a first volatile memory and stores the deallocate summary table is stored in a second volatile memory, different from the first volatile memory.
    Type: Grant
    Filed: May 10, 2023
    Date of Patent: February 11, 2025
    Assignee: Kioxia Corporation
    Inventors: Saswati Das, Manish Kadam
  • Patent number: 12153813
    Abstract: Systems, methods, non-transitory computer-readable media for maintaining predictable latency among tenants. One system includes a die group segregator configured to segregate superblock IDs based on die group IDs. The system further includes a die group manager configured to identify superblocks of the superblock IDs in a first Quality of Service (QOS) domain of a first die group ID and select a first superblock in the first QoS domain based on weights of atomic data unit (ADUs) within each WLSTR. The system further includes a command processing system configured to schedule programming of the at least one WLSTR of the first QoS domain or a second QoS domain to program to a die group, wherein scheduling is based on a first QoS domain weight and a second QoS domain weight, segregate write commands into die units and provide the plural scheduled write commands to a die manager.
    Type: Grant
    Filed: April 3, 2023
    Date of Patent: November 26, 2024
    Assignee: KIOXIA CORPORATION
    Inventor: Saswati Das
  • Publication number: 20240329864
    Abstract: Systems, methods, non-transitory computer-readable media for maintaining predictable latency among tenants. One system includes a die group segregator configured to segregate superblock IDs based on die group IDs. The system further includes a die group manager configured to identify superblocks of the superblock IDs in a first Quality of Service (QoS) domain of a first die group ID and select a first superblock in the first QoS domain based on weights of atomic data unit (ADUs) within each WLSTR. The system further includes a command processing system configured to schedule programming of the at least one WLSTR of the first QoS domain or a second QoS domain to program to a die group, wherein scheduling is based on a first QoS domain weight and a second QoS domain weight, segregate write commands into die units and provide the plural scheduled write commands to a die manager.
    Type: Application
    Filed: April 3, 2023
    Publication date: October 3, 2024
    Applicant: Kioxia Corporation
    Inventor: Saswati Das
  • Publication number: 20240329879
    Abstract: Systems, methods, non-transitory computer-readable media for creating isolation between multiple domains. One system includes a VD level disperser configured to segregate new write commands based on virtual device (VD) identifiers and maintain separate VD specific in-place linked lists. The system further includes a Quality of Service (QOS) level disperser configured to segregate VD specific commands of the VD specific in-place linked lists based on each of the VD specific commands respective QoS domain identifiers and maintain separate QoS domain specific linked lists. The system further includes a superblock level disperser configured to segregate QoS domain specific commands of the QoS domain specific in-place linked lists based on each of the QoS domain specific commands respective superblock or placement identifiers, maintain separate superblock-specific in-place linked lists for each superblock or placement identifier, and provide the superblock-specific in-place linked lists to a write divider.
    Type: Application
    Filed: April 3, 2023
    Publication date: October 3, 2024
    Applicant: Kioxia Corporation
    Inventor: Saswati Das
  • Patent number: 11977773
    Abstract: A method performed by a controller of a solid-state drive (SSD) comprising splitting a logical to physical mapping table in a non-volatile semiconductor memory device of the SSD into a plurality of regions, each of the regions associated with a plurality of logical cluster addresses (LCAs), determining if the mapping table for each region contains an entry with a valid address, setting a validity status in a validity bit for a region of the plurality of regions if the mapping table for the region contains any mapped addresses, and storing the validity bit for each region in a validity bitmap table (VBT).
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: May 7, 2024
    Assignee: KIOXIA CORPORATION
    Inventors: Saswati Das, Manish Kadam
  • Patent number: 11947816
    Abstract: A method performed by a controller of a solid-state drive (SSD) comprising receiving a command from a host, the command identifying a namespace in a non-volatile semiconductor memory device of the SSD to be formatted, identifying a plurality of regions in the non-volatile semiconductor memory device corresponding to the namespace, unmapping a dummy region in a volatile semiconductor memory device of the SSD using invalid addresses, and copying the invalidated dummy region to each region of the plurality of regions of the namespace.
    Type: Grant
    Filed: September 19, 2022
    Date of Patent: April 2, 2024
    Assignee: Kioxia Corporation
    Inventor: Saswati Das
  • Publication number: 20240094928
    Abstract: A method performed by a controller of a solid-state drive (SSD) comprising receiving a command from a host, the command identifying a namespace in a non-volatile semiconductor memory device of the SSD to be formatted, identifying a plurality of regions in the non-volatile semiconductor memory device corresponding to the namespace, unmapping a dummy region in a volatile semiconductor memory device of the SSD using invalid addresses, and copying the invalidated dummy region to each region of the plurality of regions of the namespace.
    Type: Application
    Filed: September 19, 2022
    Publication date: March 21, 2024
    Inventor: Saswati DAS
  • Patent number: 11797452
    Abstract: Various implementations described herein relate to systems and methods for dynamically managing buffers of a storage device, including receiving, by a controller of the storage device from a host, information indicative of a frequency by which data stored in the storage device is accessed, and in response to receiving the information determining, by the controller, the order by which read buffers of the storage device are allocated for a next read command. The NAND read count of virtual Word-Lines (WLs) are also used to cache more frequently accessed WLs, thus proactively reducing read disturb and consequently increasing NAND reliability and NAND life.
    Type: Grant
    Filed: July 18, 2022
    Date of Patent: October 24, 2023
    Assignee: KIOXIA CORPORATION
    Inventors: Saswati Das, Manish Kadam, Neil Buxton
  • Publication number: 20230273734
    Abstract: The present invention is directed to an SSD that stores data in a plurality of regions of the SSD, each of the regions associated with a plurality of logical cluster addresses. The SSD also sets a deallocation status of each of the plurality of regions in a deallocate flag bitmap and sets a deallocation status of one or more sections of the deallocate flag bitmap in a deallocate summary table, wherein each of the one or more sections corresponds to more than one of the plurality of regions. In response to a shutdown or loss of power event, The SSD writes to non-volatile memory only sections of the deallocation flag bitmap with a predetermined deallocation status in the deallocate summary table. The SSD stores the deallocate flag bitmap is stored in a first volatile memory and stores the deallocate summary table is stored in a second volatile memory, different from the first volatile memory.
    Type: Application
    Filed: May 10, 2023
    Publication date: August 31, 2023
    Inventors: Saswati DAS, Manish KADAM
  • Patent number: 11669254
    Abstract: The present invention is directed to an SSD that stores data in a plurality of regions of the SSD, each of the regions associated with a plurality of logical cluster addresses. The SSD also sets a deallocation status of each of the plurality of regions in a deallocate flag bitmap and sets a deallocation status of one or more sections of the deallocate flag bitmap in a deallocate summary table, wherein each of the one or more sections corresponds to more than one of the plurality of regions. In response to a shutdown or loss of power event. The SSD writes to non-volatile memory only sections of the deallocation flag bitmap with a predetermined deallocation status in the deallocate summary table. The SSD stores the deallocate flag bitmap is stored in a first volatile memory and stores the deallocate summary table is stored in a second volatile memory, different from the first volatile memory.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: June 6, 2023
    Assignee: Kioxia Corporation
    Inventors: Saswati Das, Manish Kadam
  • Publication number: 20230095644
    Abstract: The present invention is directed to an SSD that stores data in a plurality of regions of the SSD, each of the regions associated with a plurality of logical cluster addresses. The SSD also sets a deallocation status of each of the plurality of regions in a deallocate flag bitmap and sets a deallocation status of one or more sections of the deallocate flag bitmap in a deallocate summary table, wherein each of the one or more sections corresponds to more than one of the plurality of regions. In response to a shutdown or loss of power event, The SSD writes to non-volatile memory only sections of the deallocation flag bitmap with a predetermined deallocation status in the deallocate summary table. The SSD stores the deallocate flag bitmap is stored in a first volatile memory and stores the deallocate summary table is stored in a second volatile memory, different from the first volatile memory.
    Type: Application
    Filed: September 30, 2021
    Publication date: March 30, 2023
    Inventors: Saswati DAS, Manish KADAM
  • Publication number: 20230096420
    Abstract: A method performed by a controller of a solid-state drive (SSD) comprising splitting a logical to physical mapping table in a non-volatile semiconductor memory device of the SSD into a plurality of regions, each of the regions associated with a plurality of logical cluster addresses (LCAs), determining if the mapping table for each region contains an entry with a valid address, setting a validity status in a validity bit for a region of the plurality of regions if the mapping table for the region contains any mapped addresses, and storing the validity bit for each region in a validity bitmap table (VBT).
    Type: Application
    Filed: September 30, 2021
    Publication date: March 30, 2023
    Inventors: Saswati DAS, Manish KADAM
  • Publication number: 20220350746
    Abstract: Various implementations described herein relate to systems and methods for dynamically managing buffers of a storage device, including receiving, by a controller of the storage device from a host, information indicative of a frequency by which data stored in the storage device is accessed, and in response to receiving the information determining, by the controller, the order by which read buffers of the storage device are allocated for a next read command. The NAND read count of virtual Word-Lines (WLs) are also used to cache more frequently accessed WLs, thus proactively reducing read disturb and consequently increasing NAND reliability and NAND life.
    Type: Application
    Filed: July 18, 2022
    Publication date: November 3, 2022
    Applicant: Kioxia Corporation
    Inventors: Saswati Das, Manish Kadam, Neil Buxton
  • Patent number: 11392499
    Abstract: Various implementations described herein relate to systems and methods for dynamically managing buffers of a storage device, including receiving, by a controller of the storage device from a host, information indicative of a frequency by which data stored in the storage device is accessed, and in response to receiving the information determining, by the controller, the order by which read buffers of the storage device are allocated for a next read command. The NAND read count of virtual Word-Lines (WLs) are also used to cache more frequently accessed WLs, thus proactively reducing read disturb and consequently increasing NAND reliability and NAND life.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: July 19, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Saswati Das, Manish Kadam, Neil Buxton
  • Publication number: 20220091984
    Abstract: Various implementations described herein relate to systems and methods for dynamically managing buffers of a storage device, including receiving, by a controller of the storage device from a host, information indicative of a frequency by which data stored in the storage device is accessed, and in response to receiving the information determining, by the controller, the order by which read buffers of the storage device are allocated for a next read command. The NAND read count of virtual Word-Lines (WLs) are also used to cache more frequently accessed WLs, thus proactively reducing read disturb and consequently increasing NAND reliability and NAND life.
    Type: Application
    Filed: September 18, 2020
    Publication date: March 24, 2022
    Applicant: Kioxia Corporation
    Inventors: Saswati DAS, Manish KADAM, Neil BUXTON
  • Patent number: 10909030
    Abstract: In an SSD including a host interface, controller, non-volatile memory coupled to the controller, and volatile memory, data is stored in non-volatile memory in clusters having a cluster start address and a cluster end address. A mapping table is maintained in volatile memory, which indicates by a trim signature deallocated clusters in non-volatile memory. The trim table is populated with deallocated ranges and an associated offset within the non-volatile memory. The controller receives from the host interface a sequence of commands including a deallocate command including at least one address range including a start address and an end address, or a start address and a length of the address range. The controller processes the deallocate command by selecting one or both of a write-to-non-volatile-memory action and a record-to-volatile-memory action. In cases of power failure, the mapping table is restored for deallocated ranges at specific offsets recorded in the trim table.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: February 2, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Girish Desai, Saswati Das, Senthil Thangaraj, Barada Mishra, Julien Magretts, Philip Rose
  • Publication number: 20200081830
    Abstract: In an SSD including a host interface, controller, non-volatile memory coupled to the controller, and volatile memory, data is stored in non-volatile memory in clusters having a cluster start address and a cluster end address. A mapping table is maintained in volatile memory, which indicates by a trim signature deallocated clusters in non-volatile memory. The trim table is populated with deallocated ranges and an associated offset within the non-volatile memory. The controller receives from the host interface a sequence of commands including a deallocate command including at least one address range including a start address and an end address, or a start address and a length of the address range. The controller processes the deallocate command by selecting one or both of a write-to-non-volatile-memory action and a record-to-volatile-memory action. In cases of power failure, the mapping table is restored for deallocated ranges at specific offsets recorded in the trim table.
    Type: Application
    Filed: September 11, 2018
    Publication date: March 12, 2020
    Inventors: Girish Desai, Saswati Das, Senthil Thangaraj, Barada Mishra, Julien Magretts, Philip Rose