Patents by Inventor Saswati Das
Saswati Das has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12236138Abstract: Systems, methods, non-transitory computer-readable media for creating isolation between multiple domains. One system includes a VD level disperser configured to segregate new write commands based on virtual device (VD) identifiers and maintain separate VD specific in-place linked lists. The system further includes a Quality of Service (QOS) level disperser configured to segregate VD specific commands of the VD specific in-place linked lists based on each of the VD specific commands respective QoS domain identifiers and maintain separate QoS domain specific linked lists. The system further includes a superblock level disperser configured to segregate QoS domain specific commands of the QoS domain specific in-place linked lists based on each of the QoS domain specific commands respective superblock or placement identifiers, maintain separate superblock-specific in-place linked lists for each superblock or placement identifier, and provide the superblock-specific in-place linked lists to a write divider.Type: GrantFiled: April 3, 2023Date of Patent: February 25, 2025Assignee: KIOXIA CORPORATIONInventor: Saswati Das
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Patent number: 12223187Abstract: The present invention is directed to an SSD that stores data in a plurality of regions of the SSD, each of the regions associated with a plurality of logical cluster addresses. The SSD also sets a deallocation status of each of the plurality of regions in a deallocate flag bitmap and sets a deallocation status of one or more sections of the deallocate flag bitmap in a deallocate summary table, wherein each of the one or more sections corresponds to more than one of the plurality of regions. In response to a shutdown or loss of power event, The SSD writes to non-volatile memory only sections of the deallocation flag bitmap with a predetermined deallocation status in the deallocate summary table. The SSD stores the deallocate flag bitmap is stored in a first volatile memory and stores the deallocate summary table is stored in a second volatile memory, different from the first volatile memory.Type: GrantFiled: May 10, 2023Date of Patent: February 11, 2025Assignee: Kioxia CorporationInventors: Saswati Das, Manish Kadam
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Patent number: 12153813Abstract: Systems, methods, non-transitory computer-readable media for maintaining predictable latency among tenants. One system includes a die group segregator configured to segregate superblock IDs based on die group IDs. The system further includes a die group manager configured to identify superblocks of the superblock IDs in a first Quality of Service (QOS) domain of a first die group ID and select a first superblock in the first QoS domain based on weights of atomic data unit (ADUs) within each WLSTR. The system further includes a command processing system configured to schedule programming of the at least one WLSTR of the first QoS domain or a second QoS domain to program to a die group, wherein scheduling is based on a first QoS domain weight and a second QoS domain weight, segregate write commands into die units and provide the plural scheduled write commands to a die manager.Type: GrantFiled: April 3, 2023Date of Patent: November 26, 2024Assignee: KIOXIA CORPORATIONInventor: Saswati Das
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Publication number: 20240329864Abstract: Systems, methods, non-transitory computer-readable media for maintaining predictable latency among tenants. One system includes a die group segregator configured to segregate superblock IDs based on die group IDs. The system further includes a die group manager configured to identify superblocks of the superblock IDs in a first Quality of Service (QoS) domain of a first die group ID and select a first superblock in the first QoS domain based on weights of atomic data unit (ADUs) within each WLSTR. The system further includes a command processing system configured to schedule programming of the at least one WLSTR of the first QoS domain or a second QoS domain to program to a die group, wherein scheduling is based on a first QoS domain weight and a second QoS domain weight, segregate write commands into die units and provide the plural scheduled write commands to a die manager.Type: ApplicationFiled: April 3, 2023Publication date: October 3, 2024Applicant: Kioxia CorporationInventor: Saswati Das
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Publication number: 20240329879Abstract: Systems, methods, non-transitory computer-readable media for creating isolation between multiple domains. One system includes a VD level disperser configured to segregate new write commands based on virtual device (VD) identifiers and maintain separate VD specific in-place linked lists. The system further includes a Quality of Service (QOS) level disperser configured to segregate VD specific commands of the VD specific in-place linked lists based on each of the VD specific commands respective QoS domain identifiers and maintain separate QoS domain specific linked lists. The system further includes a superblock level disperser configured to segregate QoS domain specific commands of the QoS domain specific in-place linked lists based on each of the QoS domain specific commands respective superblock or placement identifiers, maintain separate superblock-specific in-place linked lists for each superblock or placement identifier, and provide the superblock-specific in-place linked lists to a write divider.Type: ApplicationFiled: April 3, 2023Publication date: October 3, 2024Applicant: Kioxia CorporationInventor: Saswati Das
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Patent number: 11977773Abstract: A method performed by a controller of a solid-state drive (SSD) comprising splitting a logical to physical mapping table in a non-volatile semiconductor memory device of the SSD into a plurality of regions, each of the regions associated with a plurality of logical cluster addresses (LCAs), determining if the mapping table for each region contains an entry with a valid address, setting a validity status in a validity bit for a region of the plurality of regions if the mapping table for the region contains any mapped addresses, and storing the validity bit for each region in a validity bitmap table (VBT).Type: GrantFiled: September 30, 2021Date of Patent: May 7, 2024Assignee: KIOXIA CORPORATIONInventors: Saswati Das, Manish Kadam
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Patent number: 11947816Abstract: A method performed by a controller of a solid-state drive (SSD) comprising receiving a command from a host, the command identifying a namespace in a non-volatile semiconductor memory device of the SSD to be formatted, identifying a plurality of regions in the non-volatile semiconductor memory device corresponding to the namespace, unmapping a dummy region in a volatile semiconductor memory device of the SSD using invalid addresses, and copying the invalidated dummy region to each region of the plurality of regions of the namespace.Type: GrantFiled: September 19, 2022Date of Patent: April 2, 2024Assignee: Kioxia CorporationInventor: Saswati Das
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Publication number: 20240094928Abstract: A method performed by a controller of a solid-state drive (SSD) comprising receiving a command from a host, the command identifying a namespace in a non-volatile semiconductor memory device of the SSD to be formatted, identifying a plurality of regions in the non-volatile semiconductor memory device corresponding to the namespace, unmapping a dummy region in a volatile semiconductor memory device of the SSD using invalid addresses, and copying the invalidated dummy region to each region of the plurality of regions of the namespace.Type: ApplicationFiled: September 19, 2022Publication date: March 21, 2024Inventor: Saswati DAS
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Patent number: 11797452Abstract: Various implementations described herein relate to systems and methods for dynamically managing buffers of a storage device, including receiving, by a controller of the storage device from a host, information indicative of a frequency by which data stored in the storage device is accessed, and in response to receiving the information determining, by the controller, the order by which read buffers of the storage device are allocated for a next read command. The NAND read count of virtual Word-Lines (WLs) are also used to cache more frequently accessed WLs, thus proactively reducing read disturb and consequently increasing NAND reliability and NAND life.Type: GrantFiled: July 18, 2022Date of Patent: October 24, 2023Assignee: KIOXIA CORPORATIONInventors: Saswati Das, Manish Kadam, Neil Buxton
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Publication number: 20230273734Abstract: The present invention is directed to an SSD that stores data in a plurality of regions of the SSD, each of the regions associated with a plurality of logical cluster addresses. The SSD also sets a deallocation status of each of the plurality of regions in a deallocate flag bitmap and sets a deallocation status of one or more sections of the deallocate flag bitmap in a deallocate summary table, wherein each of the one or more sections corresponds to more than one of the plurality of regions. In response to a shutdown or loss of power event, The SSD writes to non-volatile memory only sections of the deallocation flag bitmap with a predetermined deallocation status in the deallocate summary table. The SSD stores the deallocate flag bitmap is stored in a first volatile memory and stores the deallocate summary table is stored in a second volatile memory, different from the first volatile memory.Type: ApplicationFiled: May 10, 2023Publication date: August 31, 2023Inventors: Saswati DAS, Manish KADAM
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Patent number: 11669254Abstract: The present invention is directed to an SSD that stores data in a plurality of regions of the SSD, each of the regions associated with a plurality of logical cluster addresses. The SSD also sets a deallocation status of each of the plurality of regions in a deallocate flag bitmap and sets a deallocation status of one or more sections of the deallocate flag bitmap in a deallocate summary table, wherein each of the one or more sections corresponds to more than one of the plurality of regions. In response to a shutdown or loss of power event. The SSD writes to non-volatile memory only sections of the deallocation flag bitmap with a predetermined deallocation status in the deallocate summary table. The SSD stores the deallocate flag bitmap is stored in a first volatile memory and stores the deallocate summary table is stored in a second volatile memory, different from the first volatile memory.Type: GrantFiled: September 30, 2021Date of Patent: June 6, 2023Assignee: Kioxia CorporationInventors: Saswati Das, Manish Kadam
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Publication number: 20230095644Abstract: The present invention is directed to an SSD that stores data in a plurality of regions of the SSD, each of the regions associated with a plurality of logical cluster addresses. The SSD also sets a deallocation status of each of the plurality of regions in a deallocate flag bitmap and sets a deallocation status of one or more sections of the deallocate flag bitmap in a deallocate summary table, wherein each of the one or more sections corresponds to more than one of the plurality of regions. In response to a shutdown or loss of power event, The SSD writes to non-volatile memory only sections of the deallocation flag bitmap with a predetermined deallocation status in the deallocate summary table. The SSD stores the deallocate flag bitmap is stored in a first volatile memory and stores the deallocate summary table is stored in a second volatile memory, different from the first volatile memory.Type: ApplicationFiled: September 30, 2021Publication date: March 30, 2023Inventors: Saswati DAS, Manish KADAM
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Publication number: 20230096420Abstract: A method performed by a controller of a solid-state drive (SSD) comprising splitting a logical to physical mapping table in a non-volatile semiconductor memory device of the SSD into a plurality of regions, each of the regions associated with a plurality of logical cluster addresses (LCAs), determining if the mapping table for each region contains an entry with a valid address, setting a validity status in a validity bit for a region of the plurality of regions if the mapping table for the region contains any mapped addresses, and storing the validity bit for each region in a validity bitmap table (VBT).Type: ApplicationFiled: September 30, 2021Publication date: March 30, 2023Inventors: Saswati DAS, Manish KADAM
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Publication number: 20220350746Abstract: Various implementations described herein relate to systems and methods for dynamically managing buffers of a storage device, including receiving, by a controller of the storage device from a host, information indicative of a frequency by which data stored in the storage device is accessed, and in response to receiving the information determining, by the controller, the order by which read buffers of the storage device are allocated for a next read command. The NAND read count of virtual Word-Lines (WLs) are also used to cache more frequently accessed WLs, thus proactively reducing read disturb and consequently increasing NAND reliability and NAND life.Type: ApplicationFiled: July 18, 2022Publication date: November 3, 2022Applicant: Kioxia CorporationInventors: Saswati Das, Manish Kadam, Neil Buxton
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Patent number: 11392499Abstract: Various implementations described herein relate to systems and methods for dynamically managing buffers of a storage device, including receiving, by a controller of the storage device from a host, information indicative of a frequency by which data stored in the storage device is accessed, and in response to receiving the information determining, by the controller, the order by which read buffers of the storage device are allocated for a next read command. The NAND read count of virtual Word-Lines (WLs) are also used to cache more frequently accessed WLs, thus proactively reducing read disturb and consequently increasing NAND reliability and NAND life.Type: GrantFiled: September 18, 2020Date of Patent: July 19, 2022Assignee: KIOXIA CORPORATIONInventors: Saswati Das, Manish Kadam, Neil Buxton
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Publication number: 20220091984Abstract: Various implementations described herein relate to systems and methods for dynamically managing buffers of a storage device, including receiving, by a controller of the storage device from a host, information indicative of a frequency by which data stored in the storage device is accessed, and in response to receiving the information determining, by the controller, the order by which read buffers of the storage device are allocated for a next read command. The NAND read count of virtual Word-Lines (WLs) are also used to cache more frequently accessed WLs, thus proactively reducing read disturb and consequently increasing NAND reliability and NAND life.Type: ApplicationFiled: September 18, 2020Publication date: March 24, 2022Applicant: Kioxia CorporationInventors: Saswati DAS, Manish KADAM, Neil BUXTON
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Patent number: 10909030Abstract: In an SSD including a host interface, controller, non-volatile memory coupled to the controller, and volatile memory, data is stored in non-volatile memory in clusters having a cluster start address and a cluster end address. A mapping table is maintained in volatile memory, which indicates by a trim signature deallocated clusters in non-volatile memory. The trim table is populated with deallocated ranges and an associated offset within the non-volatile memory. The controller receives from the host interface a sequence of commands including a deallocate command including at least one address range including a start address and an end address, or a start address and a length of the address range. The controller processes the deallocate command by selecting one or both of a write-to-non-volatile-memory action and a record-to-volatile-memory action. In cases of power failure, the mapping table is restored for deallocated ranges at specific offsets recorded in the trim table.Type: GrantFiled: September 11, 2018Date of Patent: February 2, 2021Assignee: Toshiba Memory CorporationInventors: Girish Desai, Saswati Das, Senthil Thangaraj, Barada Mishra, Julien Magretts, Philip Rose
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Publication number: 20200081830Abstract: In an SSD including a host interface, controller, non-volatile memory coupled to the controller, and volatile memory, data is stored in non-volatile memory in clusters having a cluster start address and a cluster end address. A mapping table is maintained in volatile memory, which indicates by a trim signature deallocated clusters in non-volatile memory. The trim table is populated with deallocated ranges and an associated offset within the non-volatile memory. The controller receives from the host interface a sequence of commands including a deallocate command including at least one address range including a start address and an end address, or a start address and a length of the address range. The controller processes the deallocate command by selecting one or both of a write-to-non-volatile-memory action and a record-to-volatile-memory action. In cases of power failure, the mapping table is restored for deallocated ranges at specific offsets recorded in the trim table.Type: ApplicationFiled: September 11, 2018Publication date: March 12, 2020Inventors: Girish Desai, Saswati Das, Senthil Thangaraj, Barada Mishra, Julien Magretts, Philip Rose