Patents by Inventor Satchit Jain

Satchit Jain has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7027057
    Abstract: An interface between an accelerated graphics port graphics controller (AGP-GC) and a core controller to prevent entry into a low power state from interfering with transfers to or from the AGP-GC that have been requested but not completed. The core controller can communicate to the AGP-GC an intent to enter a low power state, while the AGP-GC can communicate to the core controller the busy status of the AGP-GC. When the AGP-GC receives notice of an intent to enter a low power state, it can stop issuing requests to the core controller. When the core controller detects that the AGP-GC is busy, the core controller can postpone entry into the low power state until the AGP-GC completes any requests that are in progress. In an alternate use of the interface, if the AGP-GC wishes to make a request during a low power state, it can signal the core controller of this need by indicating a busy status, which can trigger the core controller to initiate an exit from the low power state.
    Type: Grant
    Filed: August 12, 2003
    Date of Patent: April 11, 2006
    Assignee: Intel Corporation
    Inventors: Satchit Jain, Debra T. Cohen, Leslie E. Cline, Barnes Cooper, Anil V. Nanduri
  • Publication number: 20040225907
    Abstract: A system has a processor with multiple states, including an awake state and a sleep state, a memory subsystem including a memory controller and memory devices, and a second memory. The system uses software in the second memory to initialize the memory controller upon a transition from a sleep state to an awake state. The system detects a wake event trigger, and in response to the wake event trigger, executes software stored in the second memory to initialize the memory controller, and then executes software out of the first memory after the initialization.
    Type: Application
    Filed: June 8, 2004
    Publication date: November 11, 2004
    Applicant: Intel Corporation
    Inventors: Satchit Jain, Sung-Soo Cho
  • Patent number: 6782472
    Abstract: A system has a processor with multiple states, including an awake state and a sleep state, a memory subsystem including a memory controller and memory devices, and a second memory. The system uses software in the second memory to initialize the memory controller upon a transition from a sleep state to an awake state. The system detects a wake event trigger, and in response to the wake event trigger, executes software stored in the second memory to initialize the memory controller, and then executes software out of the first memory after the initialization.
    Type: Grant
    Filed: March 12, 2003
    Date of Patent: August 24, 2004
    Assignee: Intel Corporation
    Inventors: Satchit Jain, Sung-Soo Cho
  • Patent number: 6738068
    Abstract: An interface between an accelerated graphics port graphics controller (AGP-GC) and a core controller to prevent entry into a low power state from interfering with transfers to or from the AGP-GC that have been requested but not completed. The core controller can communicate to the AGP-GC an intent to enter a low power state, while the AGP-GC can communicate to the core controller the busy status of the AGP-GC. When the AGP-GC receives notice of an intent to enter a low power state, it can stop issuing requests to the core controller. When the core controller detects that the AGP-GC is busy, the core controller can postpone entry into the low power state until the AGP-GC completes any requests that are in progress. In an alternate use of the interface, if the AGP-GC wishes to make a request during a low power state, it can signal the core controller of this need by indicating a busy status, which can trigger the core controller to initiate an exit from the low power state.
    Type: Grant
    Filed: December 29, 2000
    Date of Patent: May 18, 2004
    Assignee: Intel Corporation
    Inventors: Debra T. Cohen, Leslie E. Cline, Barnes Cooper, Satchit Jain, Anil V. Nanduri
  • Publication number: 20040032414
    Abstract: An interface between an accelerated graphics port graphics controller (AGP-GC) and a core controller to prevent entry into a low power state from interfering with transfers to or from the AGP-GC that have been requested but not completed. The core controller can communicate to the AGP-GC an intent to enter a low power state, while the AGP-GC can communicate to the core controller the busy status of the AGP-GC. When the AGP-GC receives notice of an intent to enter a low power state, it can stop issuing requests to the core controller. When the core controller detects that the AGP-GC is busy, the core controller can postpone entry into the low power state until the AGP-GC completes any requests that are in progress. In an alternate use of the interface, if the AGP-GC wishes to make a request during a low power state, it can signal the core controller of this need by indicating a busy status, which can trigger the core controller to initiate an exit from the low power state.
    Type: Application
    Filed: August 12, 2003
    Publication date: February 19, 2004
    Inventors: Satchit Jain, Debra T. Cohen, Leslie E. Cline, Barnes Cooper, Anil V. Nanduri
  • Patent number: 6633987
    Abstract: A mechanism for conserving power consumption includes a processor, a memory, and a memory control hub (“MCH”). The memory is coupled to the processor and MCH is also coupled to the processor. MCH is further configured to switch between at least two power consumption modes for conserving power consumption.
    Type: Grant
    Filed: March 24, 2000
    Date of Patent: October 14, 2003
    Assignee: Intel Corporation
    Inventors: Satchit Jain, Siripong Sritanyaratana
  • Publication number: 20030172313
    Abstract: A system has a processor with multiple states, including an awake state and a sleep state, a memory subsystem including a memory controller and memory devices, and a second memory. The system uses software in the second memory to initialize the memory controller upon a transition from a sleep state to an awake state. The system detects a wake event trigger, and in response to the wake event trigger, executes software stored in the second memory to initialize the memory controller, and then executes software out of the first memory after the initialization.
    Type: Application
    Filed: March 12, 2003
    Publication date: September 11, 2003
    Applicant: Intel Corporation, a California corporation
    Inventors: Satchit Jain, Sung-Soo Cho
  • Patent number: 6574738
    Abstract: An integrated circuit contains a central processing unit (“CPU”), a graphic control hub (“GCH”), a memory control hub (“MCH”), and a phase lock loop (“PLL”). The GCH, MCH, and PLL are coupled to the CPU. The MCH controls memory transactions. The PLL is configured to allow the CPU to operate at more than one power consumption states.
    Type: Grant
    Filed: July 11, 2002
    Date of Patent: June 3, 2003
    Assignee: Intel Corporation
    Inventors: Satchit Jain, Sun-Soo Cho
  • Publication number: 20030101361
    Abstract: A mechanism for conserving power consumption includes a processor, a memory, and a memory control hub (“MCH”). The memory is coupled to the processor and MCH is also coupled to the processor. MCH is further configured to switch between at least two power consumption modes for conversing power consumption.
    Type: Application
    Filed: March 24, 2000
    Publication date: May 29, 2003
    Inventors: Satchit Jain, Siripong Sritanyaratana
  • Patent number: 6571333
    Abstract: A system has a processor with multiple states, including an awake state and a sleep state, a memory subsystem including a memory controller and memory devices, and a second memory. The system uses software in the second memory to initialize the memory controller upon a transition from a sleep state to an awake state. The system detects a wake event trigger, and in response to the wake event trigger, executes software stored in the second memory to initialize the memory controller, and then executes software out of the first memory after the initialization.
    Type: Grant
    Filed: November 5, 1999
    Date of Patent: May 27, 2003
    Assignee: Intel Corporation
    Inventors: Satchit Jain, Sung-Soo Cho
  • Publication number: 20020188884
    Abstract: An integrated circuit contains a central processing unit (“CPU”), a graphic control hub (“GCH”), a memory control hub (“MCH”), and a phase lock loop (“PLL”). The GCH, MCH, and PLL are coupled to the CPU. The MCH controls memory transactions. The PLL is configured to allow the CPU to operate at more than one power consumption states.
    Type: Application
    Filed: July 11, 2002
    Publication date: December 12, 2002
    Inventors: Satchit Jain, Sung-Soo Cho
  • Patent number: 6442697
    Abstract: An integrated circuit contains a central processing unit (“CPU”), a graphic control hub (“GCH”), a memory control hub (“MCH”), and a phase lock loop (“PLL”). The GCH, MCH, and PLL are coupled to the CPU. The MCH controls memory transactions. The PLL is configured to allow the CPU to operate at more than one power consumption states.
    Type: Grant
    Filed: March 24, 2000
    Date of Patent: August 27, 2002
    Assignee: Intel Corporation
    Inventors: Satchit Jain, Sun-Soo Cho
  • Publication number: 20020085008
    Abstract: An interface between an accelerated graphics port graphics controller (AGP-GC) and a core controller to prevent entry into a low power state from interfering with transfers to or from the AGP-GC that have been requested but not completed. The core controller can communicate to the AGP-GC an intent to enter a low power state, while the AGP-GC can communicate to the core controller the busy status of the AGP-GC. When the AGP-GC receives notice of an intent to enter a low power state, it can stop issuing requests to the core controller. When the core controller detects that the AGP-GC is busy, the core controller can postpone entry into the low power state until the AGP-GC completes any requests that are in progress. In an alternate use of the interface, if the AGP-GC wishes to make a request during a low power state, it can signal the core controller of this need by indicating a busy status, which can trigger the core controller to initiate an exit from the low power state.
    Type: Application
    Filed: December 29, 2000
    Publication date: July 4, 2002
    Inventors: Satchit Jain, Debra T Cohen, Leslie E Cline, Barnes Cooper, Anil V Nanduri