Patents by Inventor Satchitanand Jain

Satchitanand Jain has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • System for allowing multiple instructions to use the same logical registers by remapping them to separate physical segment registers when the first is being utilized
    Patent number: 5974525
    Abstract: A technique for increasing the number of physical segment registers by renaming logical segment registers into a larger register space. The remapping of the segment registers allows for instructions accessing the segment registers to be executed non-serially. The renaming of segment registers is achieved by assigning a shadow register to a segment register name. Thus, a pair of registers are physically available for a specified logical register in an instruction set to be renamed. Two bits, designated as the PSEG and SPEC bits, are used to control the remapping.
    Type: Grant
    Filed: December 5, 1997
    Date of Patent: October 26, 1999
    Assignee: Intel Corporation
    Inventors: Derrick Chu Lin, Ramamohan Rao Vakkalagadda, Satchitanand Jain, Varsha P. Tagare, Nimish H. Modi