Abstract: Circuits and methods for reducing the cost and/or power consumption of a user terminal and/or the gateway of a telecommunications system that may include a telecommunications satellite. Embodiments include “chained” feedback-regulated voltage supply circuits. These circuits substantially eliminate the need for separate regulator circuits for each regulated voltage. These circuits are designed to automatically maintain a substantially constant first voltage at a first node for a first load and maintain a substantially constant second voltage at a second node for a second load. Some disclosed configurations of these circuits may be useful to achieve greater current capability at the same voltage without requiring larger switches and higher inductor and capacitor sizes that may be needed in a single (conventional) stage voltage supply circuit.

Abstract: Circuits and methods for reducing the cost and/or power consumption of a user terminal and/or the gateway of a telecommunications system that may include a telecommunications satellite. Embodiments include “chained” feedback-regulated voltage supply circuits. These circuits substantially eliminate the need for separate regulator circuits for each regulated voltage. These circuits are designed to automatically maintain a substantially constant first voltage at a first node for a first load and maintain a substantially constant second voltage at a second node for a second load. Some disclosed configurations of these circuits may be useful to achieve greater current capability at the same voltage without requiring larger switches and higher inductor and capacitor sizes that may be needed in a single (conventional) stage voltage supply circuit.

Abstract: Circuits and methods for reducing the cost and/or power consumption of a user terminal and/or the gateway of a telecommunications system (550) that may include a telecommunications satellite. Embodiments generate a dynamic input bias signal based upon an information signal envelope (which may be pre-distorted) which is applied to the signal input of a power amplifier (PA), thus reducing average power consumption. Other embodiments further include dynamic linearization (518) of the information signal, and/or variation of the supply voltage to the power amplifier (PA) as a function of the envelope of the information signal. Another aspect is a multi-stage “chained” feedback regulated voltage supply circuit for providing two or more output voltages that may be used as alternative supply voltages to a power amplifier (PA).

Abstract: Circuits and methods for reducing the cost and/or power consumption of a user terminal and/or the gateway of a telecommunications system (550) that may include a telecommunications satellite. Embodiments generate a dynamic input bias signal based upon an information signal envelope (which may be pre-distorted) which is applied to the signal input of a power amplifier (PA), thus reducing average power consumption. Other embodiments further include dynamic linearization (518) of the information signal, and/or variation of the supply voltage to the power amplifier (PA) as a function of the envelope of the information signal. Another aspect is a multi-stage “chained” feedback regulated voltage supply circuit for providing two or more output voltages that may be used as alternative supply voltages to a power amplifier (PA).

Abstract: An electronic apparatus includes a semiconductor substrate, a circuit block disposed in and supported by the semiconductor substrate and comprising an inductor, and a discontinuous noise isolation guard ring surrounding the circuit block. The discontinuous noise isolation guard ring includes a metal ring supported by the semiconductor substrate and a ring-shaped region disposed in the semiconductor substrate, having a dopant concentration level, and electrically coupled to the metal ring, to inhibit noise in the semiconductor substrate from reaching the circuit. The metal ring has a first gap and the ring-shaped region has a second gap.

Abstract: An electronic apparatus includes a semiconductor substrate, a circuit block disposed in and supported by the semiconductor substrate and comprising an inductor, and a discontinuous noise isolation guard ring surrounding the circuit block. The discontinuous noise isolation guard ring includes a metal ring supported by the semiconductor substrate and a ring-shaped region disposed in the semiconductor substrate, having a dopant concentration level, and electrically coupled to the metal ring, to inhibit noise in the semiconductor substrate from reaching the circuit. The metal ring has a first gap and the ring-shaped region has a second gap.

Abstract: A system that includes a polyphase filter comprises first and second gm-C filters with first and second variable biasing and a bias controller coupled to the first and second gm-C filters and configured to offset the first variable biasing and corresponding first gm of the first gm-C filter relative to the second variable biasing and corresponding second gm of the second gm-C filter to thus improve image rejection in the system. A corresponding method includes processing a signal in a complex polyphase filter and controlling biasing of the first gm-C filter stage relative to the second gm-C filter stage to provide a mismatched gm and thereby improve rejection of the image signal.

Abstract: A system that includes a polyphase filter comprises first and second gm-C filters with first and second variable biasing and a bias controller coupled to the first and second gm-C filters and configured to offset the first variable biasing and corresponding first gm of the first gm-C filter relative to the second variable biasing and corresponding second gm of the second gm-C filter to thus improve image rejection in the system. A corresponding method includes processing a signal in a complex polyphase filter and controlling biasing of the first gm-C filter stage relative to the second gm-C filter stage to provide a mismatched gm and thereby improve rejection of the image signal.

Abstract: A low voltage, high bandwidth, enhanced transconductance, source follower circuit constructed from MOS FET devices, which operates in a class AB mode. The drain current of the source follower is sensed with a folded cascode device. The sensed current is multiplied by a common source device of same type (NMOS or PMOS) as the source follower, and directed to the output load. Over limit current load at the source follower drain is sensed by a common source device of the opposite type (NMOS or PMOS), which also supplies the necessary extra current to the output load. This allows. the device to supply significantly more than the quiescent current in both sourcing and sinking the output. Average power consumption for driving a given load is significantly reduced, while maintaining the large bandwidth of traditional source follower designs, and the capability for use in either voltage regulators or in a current conveyor.

Abstract: A low voltage, high bandwidth, enhanced transconductance, source follower circuit constructed from MOS FET devices, which operates in a class AB mode. The drain current of the source follower is sensed with a folded cascode device. The sensed current is multiplied by a common source device of same type (NMOS or PMOS) as the source follower, and directed to the output load. Over limit current load at the source follower drain is sensed by a common source device of the opposite type (NMOS or PMOS), which also supplies the necessary extra current to the output load. This allows the device to supply significantly more than the quiescent current in both sourcing and sinking the output. Average power consumption for driving a given load is significantly reduced, while maintaining the large bandwidth of traditional source follower designs, and the capability for use in either voltage regulators or in a current conveyor.

Abstract: A folded cascode device senses the drain current of a source follower, and a current mirror device multiplies the sensed drain current for application to an output load. The source follower and the current mirror device are preferably of the same type (e.g., both NMOS). The resulting composite source follower provides relatively wide bandwidth at relatively low power. The folded cascode allows (NMOS) source and sink control. Using current mirror feedback reduces the stability problems associated with other solutions that rely on a voltage feedback stage. Composite source followers of the present invention can be used in any traditional buffer applications, such as in operational amplifiers, regulators, or high-speed signal paths.