Patents by Inventor Satendra Pal Singh

Satendra Pal Singh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Dynamic motion vector analysis method
    Patent number: 8300697
    Abstract: The proposed Dynamic Motion Vector Analysis method applies to the motion compensation module of a video decoder system. The method analyzes the motion-vectors of a given region of picture frame and outputs a set of regions to be fetched from the reference frames stored in the external memory. The size and number of regions are decided by a hierarchical method that uses a set of user-defined input thresholds. Pre-processing of the motion vectors associated with the given region allows the method to handle reference data to be fetched from multiple reference frames in the same framework. A complementary dynamic batch (region of operation) size strategy that works along with MV-analysis is also proposed to help utilize the on-chip memory resources more efficiently.
    Type: Grant
    Filed: April 8, 2008
    Date of Patent: October 30, 2012
    Assignee: Allgo Embedded Systems Private Limited.
    Inventors: Sachin Sudhakar Farfade, Satendra Pal Singh, Kiran Rajaram, Abhay Sharma
  • DYNAMIC MOTION VECTOR ANALYSIS METHOD
    Publication number: 20100098165
    Abstract: The proposed Dynamic Motion Vector Analysis method applies to the motion compensation module of a video decoder system. The method analyzes the motion-vectors of a given region of picture frame and outputs a set of regions to be fetched from the reference frames stored in the external memory. The size and number of regions are decided by a hierarchical method that uses a set of user-defined input thresholds. Pre-processing of the motion vectors associated with the given region allows the method to handle reference data to be fetched from multiple reference frames in the same framework. A complementary dynamic batch (region of operation) size strategy that works along with MV-analysis is also proposed to help utilize the on-chip memory resources more efficiently.
    Type: Application
    Filed: April 8, 2008
    Publication date: April 22, 2010
    Applicant: ALLGO Embedded Systems Pvt. Ltd.
    Inventors: Sachin Sudhakar Farfade, Satendra Pal Singh, Kiran Rajaram, Abhay Sharma