Abstract: Provided is a memory device, a method and a system that includes a host in communication with a system memory having a driver that creates commands for writing and reading data, and the memory device in communication with the host that includes a memory array including a plurality of memory components, a device attached memory including a submission queue and a completion queue for receiving commands from the driver, and a device controller configure to communicate with the device attached memory, the host and the plurality of memory components, such that the device controller receives an interface or link from the driver indicative of commands being placed into the submission queue, and automatically executes any pending commands therein for completion.

Abstract: A system and method of using the system may comprise: a rack; a first rack server mounted within the rack; and a device including Compute Express Link (CXL) switch fabric, processing circuitry operatively coupled to the CXL switch fabric, memory operatively coupled to the CXL switch fabric, and a chassis mounted within the rack, the chassis housing the CXL switch fabric, the processing circuitry, and the memory. The processing circuitry may be configured to control the CXL switch fabric to allocate or deallocate at least a portion of the memory to or from the rack server. The chassis may be arranged at a top of the rack. The processing circuitry may further be configured to control the CXL switch fabric to allocate or deallocate at least another portion of the memory to or from another rack server.

Abstract: A system comprises a chassis; a Compute Express Link (CXL) back plane interface mounted within the chassis; a first printed circuit board housed within the chassis and connected to the CXL back plane interface, the first printed circuit board including processing circuitry, switching circuitry and a memory; and a blade server comprising a second printed circuit board housed within the chassis and connected to the CXL back plane interface. The processing circuitry is configured to control the switching circuitry to allocate at least a portion of the memory to the blade server such that a virtual machine provided by the blade server can access the allocated memory through the CXL back plane interface in addition to its own dedicated memory provided by the blade server.