Abstract: A system, method, and computer program product for performing attestation by a baseboard management controller (BMC) of target devices are provided. A data center secure control module (DC-SCM) coupled to BMC includes a PLD with an arbiter that communicates using LTPI IP over I2C with the HPM. The BMC issues MCPT requests for attestation information to target devices. The arbiter at the DC-SCM establishes a two-way communication mode over the LTPI IP with the HPM to transfer the requests to the HPM on a primary LTPI I2C channel. A PLD with an arbiter at HPM routes the requests to target devices using virtual I2C nodes. The target devices issue responses with the attestation information. The responses are routed to the arbiter of the HPM, that uses the virtual I2C nodes to route the responses over a secondary LTPI I2C channel to the DC-SCM. The DC-SCM routes the responses to the BMC.

Abstract: In one embodiment, a system includes a host system-on-chip (SoC) comprising vision processing circuitry and a camera connected to the host SoC through an Inter-Integrated Circuit (I3C) bus. The camera includes circuitry to generate image data and transmit an interrupt signal to the host SoC over the I3C bus indicating the image data is ready for transfer. The host SoC vision processing circuitry is to transmit a read message to the camera over the I3C bus based on the interrupt signal and receive a set of line payload packets including the image data over the I3C bus based on the read message.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to process touch data. An example apparatus includes machine learning accelerator circuitry to execute a machine learning algorithm on touch data from touch sensor circuitry; and determine, based on an output of the machine learning algorithm, whether a touch input corresponding to the touch data was intentional; transceiver circuitry to, after a determination that the touch input was intentional, provide touch coordinates to memory; and processor circuitry to, after the determination that the touch input was intentional: access the touch coordinates in the memory; and perform an action based on the touch coordinates.

Abstract: A system and method for providing a neural network model to an artificial intelligence (AI) field programmable gate array (FPGA) are provided. A flash memory stores a neural network model. A tunnel is created between a flash memory and a random access memory (RAM) over a multi-line serial peripheral interface (QSPI) interface. Using the tunnel, the RAM reads one or more layers of the neural network model from the flash memory and writes the one or more layers into pages in the RAM. The AI FPGA reads the one or more layers of the neural network model from the RAM over a wide input/output interface and executes the one or more layers.

Abstract: A system, method, and computer program product for communicating between a baseboard management controller (BMC) and a host processing module (HPM) are provided. A PCIe endpoint receives packets, such as TLPs, over a first communication interface from a BMC, where payloads in packets include transactions. The PCIe endpoint extracts the transactions from the payloads of packets. An address decoder decodes, using information in the transactions, addresses of the memory spaces corresponding to physical functions of the PCIe endpoint and second communication interfaces. The memory spaces store the transactions according to the decoded addresses. The second communication interface receives the transactions from the memory spaces and transmits the transactions to the HPM.

Abstract: Various techniques are provided for managing power modes (e.g., also referred to as power states) in peripheral devices connected to host devices. In one example, a method includes receiving, by an intermediate device communicatively connected between a host device and a peripheral device, a notification that the host device will transition from a high power mode to a reduced power mode. The method also includes receiving, by the intermediate device from the peripheral device, context data associated with an operational state of the peripheral device. The method also includes storing, by the intermediate device, the context data, and power gating the peripheral device by the intermediate device while the host device remains at least partially turned on in the reduced power mode. Additional embodiments are provided to restore the operational state of the peripheral device using the stored context data. Additional systems, devices, and methods are also provided.

Abstract: A system, article, and method of standards-based audio function processing has reduced memory usage by using an address mapping table.

Abstract: A system, method, and computer program product for communicating between a baseboard management controller (BMC) and a host processing module (HPM) are provided. A PCIe endpoint receives packets, such as TLPs, over a first communication interface from a BMC, where payloads in packets include transactions. The PCIe endpoint extracts the transactions from the payloads of packets. An address decoder decodes, using information in the transactions, addresses of the memory spaces corresponding to physical functions of the PCIe endpoint and second communication interfaces. The memory spaces store the transactions according to the decoded addresses. The second communication interface receives the transactions from the memory spaces and transmits the transactions to the HPM.

Abstract: System and techniques for selectable clock sources are described herein. An electronic device includes an oscillator for a first clock signal and a tap on an input signal line to a resonator for the oscillator. The tap enables receipt of a second clock signal from an external oscillator. The electronic device includes mode selection circuitry to receives a signal from a tap to an existing input line to the electronic device. The mode selection circuitry uses this signal to select the oscillator output as the clock source or the tap on the input signal line as the clock source.

Abstract: Techniques are provided for on-chip communication. A system implementing the techniques according to an embodiment includes a first virtual physical (vPhy) circuit couplable to a host through a vPhy interface and a second vPhy circuit couplable to a device, on the same chip as the host, through another vPhy interface. The system further includes a vPhy-to-vPhy interface between the vPhy circuits which includes signal lines to transmit a first data toggle signal from the first vPhy circuit to the second vPhy circuit, and a second data toggle signal from the second vPhy circuit to the first vPhy circuit. The first vPhy circuit is configured to generate the first data toggle signal based on a signal received from the host for transmission to the device. The second vPhy circuit is configured to generate the second data toggle signal based on signal received from the device for transmission to the host.

Abstract: Various techniques are provided to emulate an ambient light sensor and determine an ambient color temperature. A programmable logic device includes an image processing pipeline with hardware components configured to process an image frame received from an image capture device, ambient light sensing hardware coupled to the image processing pipeline and configured to generate an ambient light value from the image frame, and a memory configured to store the ambient light value for use by a host system processor. The host system processor may be configured to selectively adjust a brightness and/or display color settings based on the ambient light value. The programmable logic device may be configured to operate in accordance with a polling interval. User presence data comprising audio, video, and/or user input data may be collected and fused with the ambient light value for use by the host processor.

Abstract: A device system-on-a-chip (SoC) includes a streaming audio interface, a local memory, and a device controller coupled to the memory. The device controller is to decode an audio frame to generate a decoded audio frame. The audio frame is received via the streaming audio interface. The decoded audio frame is processed according to a streaming audio protocol to obtain corresponding control data and periodic streaming audio data. The control data is parsed to obtain a memory address pointer. Memory access to the local memory is performed based on the memory address pointer.

Abstract: Example methods, apparatus, systems and articles of manufacture to reduce audio streaming latency between audio and Gigabit Ethernet subsystems are disclosed herein. An example integrated circuit disclosed herein to process an audio stream associated with an endpoint device on a network includes an Ethernet subsystem to access the network and an audio subsystem to process audio data associated with the audio stream. The disclosed example integrated circuit also includes a direct hardware path between the Ethernet subsystem and the audio subsystem to exchange audio data between the Ethernet subsystem and the audio subsystem without the audio data being processed by a first software driver that is to provide access to the Ethernet subsystem or a second software driver that is to provide access to the audio subsystem.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to process touch data. An example apparatus includes machine learning accelerator circuitry to execute a machine learning algorithm on touch data from touch sensor circuitry; and determine, based on an output of the machine learning algorithm, whether a touch input corresponding to the touch data was intentional; transceiver circuitry to, after a determination that the touch input was intentional, provide touch coordinates to memory; and processor circuitry to, after the determination that the touch input was intentional: access the touch coordinates in the memory; and perform an action based on the touch coordinates.

Abstract: Described is an apparatus comprising a first interface, a second interface, a third interface, and an interconnection fabric. The first interface may transfer a first stream of data traffic. The second interface, which may be an enhanced Serial Peripheral Interface (eSPI) interface, may transfer a second stream of data traffic and a third stream of data traffic. The third interface may transfer a fourth stream of data traffic. The interconnection fabric may couple the first interface to the second interface and may couple the second interface to the third interface. The second interface may initiate a transfer of an outbound data stream from one of the second stream of data traffic or the third stream of data traffic based on an available-space credit indicator. The second interface may receive an inbound data stream based upon the outbound data stream.

Abstract: Techniques are provided for on-chip communication. A system implementing the techniques according to an embodiment includes a first virtual physical (vPhy) circuit couplable to a host through a vPhy interface and a second vPhy circuit couplable to a device, on the same chip as the host, through another vPhy interface. The system further includes a vPhy-to-vPhy interface between the vPhy circuits which includes signal lines to transmit a first data toggle signal from the first vPhy circuit to the second vPhy circuit, and a second data toggle signal from the second vPhy circuit to the first vPhy circuit. The first vPhy circuit is configured to generate the first data toggle signal based on a signal received from the host for transmission to the device. The second vPhy circuit is configured to generate the second data toggle signal based on signal received from the device for transmission to the host.

Abstract: In one embodiment, a system includes a host system-on-chip (SoC) comprising vision processing circuitry and a camera connected to the host SoC through an Inter-Integrated Circuit (I3C) bus. The camera includes circuitry to generate image data and transmit an interrupt signal to the host SoC over the I3C bus indicating the image data is ready for transfer. The host SoC vision processing circuitry is to transmit a read message to the camera over the I3C bus based on the interrupt signal and receive a set of line payload packets including the image data over the I3C bus based on the read message.

Abstract: A system, article, and method of standards-based audio function processing has reduced memory usage by using an address mapping table.

Abstract: The disclosure generally provides methods, systems and apparatus for functional safety systems. Specifically, the disclosure relates to validating functional safety warnings that may be communicated to an operator. Such warnings may include safety warning chimes.

Abstract: System and techniques for selectable clock sources are described herein. An electronic device includes an oscillator for a first clock signal and a tap on an input signal line to a resonator for the oscillator. The tap enables receipt of a second clock signal from an external oscillator. The electronic device includes mode selection circuitry to receives a signal from a tap to an existing input line to the electronic device. The mode selection circuitry uses this signal to select the oscillator output as the clock source or the tap on the input signal line as the clock source.