Abstract: A method for configuration of an Auxiliary Processing Unit (APU) of multiprocessor system is presented. The multiprocessor system has at least a Main Processing Unit (MPU) coupled to the APU via a communication link. The APU has at least a first memory and a second memory. The method includes a plurality of steps. At step the first memory is divided into an application sector, a boot sector and a common sector. At another step interrupts of the APU except interrupt/s that is/are being received via the communication link are disabled. At a further step interrupt vector/s pertaining to the communication link is/are mapped to the boot sector of the first memory. At another step a configuration code is received selectively into the application sector of the first memory and into the second memory. At a further step the interrupt/s that is/are being received via the communication link are disabled. At a further step the common sector of the first memory is updated from the second memory.

Abstract: The proposed technique provides simultaneous read and writes from a display controller using low-cost SDRAMs. This is achieved, in one example embodiment, by receiving a sequence of video frames at a first variable frame rate. A first video frame is then written in a first single-ported memory. The first video frame is then read from the first single-ported memory upon completing the writing of the first video frame in the first single-ported memory. The reading of the first video frame is then repeated from the first single-ported memory to maintain a second frame rate. The second frame rate is higher than the first variable frame rate. A second video frame is then written in a second single-ported memory upon completing the writing of the first video frame in the first single-ported memory such that the writing of the first video frame and the second video frame is at the first variable frame rate.

Abstract: A method for configuration of an Auxiliary Processing Unit (APU) of multiprocessor system is presented. The multiprocessor system has at least a Main Processing Unit (MPU) coupled to the APU via a communication link. The APU has at least a first memory and a second memory. The method includes a plurality of steps. At step the first memory is divided into an application sector, a boot sector and a common sector. At another step interrupts of the APU except interrupt/s that is/are being received via the communication link are disabled. At a further step interrupt vector/s pertaining to the communication link is/are mapped to the boot sector of the first memory. At another step a configuration code is received selectively into the application sector of the first memory and into the second memory. At a further step the interrupt/s that is/are being received via the communication link are disabled. At a further step the common sector of the first memory is updated from the second memory.

Abstract: The proposed technique provides simultaneous read and writes from a display controller using low-cost SDRAMs. This is achieved, in one example embodiment, by receiving a sequence of video frames at a first variable frame rate. A first video frame is then written in a first single-ported memory. The first video frame is then read from the first single-ported memory upon completing the writing of the first video frame in the first single-ported memory. The reading of the first video frame is then repeated from the first single-ported memory to maintain a second frame rate. The second frame rate is higher than the first variable frame rate. A second video frame is then written in a second single-ported memory upon completing the writing of the first video frame in the first single-ported memory such that the writing of the first video frame and the second video frame is at the first variable frame rate.