Patents by Inventor Sathish Kumar Radhakrishnan

Sathish Kumar Radhakrishnan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8812889
    Abstract: Controlling access to memory includes receiving a plurality of memory access requests and assigning corresponding time values to each. The assigned time values are adjusted based upon a clock pulse and a priority access list is generated. Factors consider include missed access deadlines, closeness to missing access deadlines, and whether a page is open. The highest ranked client is then passed to a sequencer to allow the requested access. Time values may be assigned and adjusted according to client ID or client type (latency or bandwidth). A plurality of power modes of operation are defined wherein operation in a selected power mode of operation is based at least in part on the assigned or adjusted time values. The processing is performed in hardware in parallel (at the same time) by associated logic circuits.
    Type: Grant
    Filed: May 5, 2010
    Date of Patent: August 19, 2014
    Assignee: Broadcom Corporation
    Inventors: Mark N. Fullerton, Sathish Kumar Radhakrishnan, Brent Mulholland, Ravi S. Setty
  • Publication number: 20110276817
    Abstract: Controlling access to memory includes receiving a plurality of memory access requests and assigning corresponding time values to each. The assigned time values are adjusted based upon a clock pulse and a priority access list is generated. Factors consider include missed access deadlines, closeness to missing access deadlines, and whether a page is open. The highest ranked client is then passed to a sequencer to allow the requested access. Time values may be assigned and adjusted according to client ID or client type (latency or bandwidth). A plurality of power modes of operation are defined wherein operation in a selected power mode of operation is based at least in part on the assigned or adjusted time values. The processing is performed in hardware in parallel (at the same time) by associated logic circuits.
    Type: Application
    Filed: May 5, 2010
    Publication date: November 10, 2011
    Applicant: BROADCOM CORPORATION
    Inventors: Mark N. Fullerton, Sathish Kumar Radhakrishnan, Brent Mulholland, Ravi S. Setty
  • Publication number: 20110276766
    Abstract: Controlling access to memory includes receiving a plurality of memory access requests and assigning corresponding time values to each. The assigned time values are adjusted based upon a clock pulse and a priority access list is generated. Factors consider include missed access deadlines, closeness to missing access deadlines, and whether a page is open. The highest ranked client is then passed to a sequencer to allow the requested access. Time values may be assigned and adjusted according to client ID or client type (latency or bandwidth). A plurality of power modes of operation are defined wherein operation in a selected power mode of operation is based at least in part on the assigned or adjusted time values. The processing is performed in hardware in parallel (at the same time) by associated logic circuits.
    Type: Application
    Filed: May 5, 2010
    Publication date: November 10, 2011
    Applicant: BROADCOM CORPORATION
    Inventors: Mark N. Fullerton, Sathish Kumar Radhakrishnan, Brent Mulholland, Ravi S. Setty, Lance Flake, Vinay Bhasin
  • Patent number: 8022966
    Abstract: A video, audio and graphics system uses multiple transport processors to receive in-band and out-of-band MPEG Transport streams, to perform PID and section filtering as well as DVB and DES decryption and to de-multiplex them. The system processes the PES into digital audio, MPEG video and message data. The system is capable of decoding multiple MPEG SLICEs concurrently. Graphics windows are blended in parallel, and blended with video using alpha blending. During graphics processing, a single-port SRAM is used equivalently as a dual-port SRAM. The video may include both analog video, e.g., NTSC/PAL/SECAM/S-video, and digital video, e.g., MPEG-2 video in SDTV or HDTV format. The system has a reduced memory mode in which video images are reduced in half in horizontal direction only during decoding. The system is capable of receiving and processing digital audio signals such as MPEG Layer 1 and Layer 2 audio and Dolby AC-3 audio, as well as PCM audio signals. The system includes a memory controller.
    Type: Grant
    Filed: December 30, 2009
    Date of Patent: September 20, 2011
    Assignee: Broadcom Corporation
    Inventors: Alexander G. MacInnis, Chengfuh Jeffrey Tang, Xiaodong Xie, Greg A. Kranawetter, Vivian Hsiun, Francis Cheung, Sandeep Bhatia, Ramanujan Valmiki, Sathish Kumar Radhakrishnan
  • Patent number: 7848432
    Abstract: Presented herein are systems and methods for efficiently storing macroblocks in DRAM. The macroblocks are stored contiguously allowing each macroblock to be written and overwritten in a single write transaction. Additionally, in one embodiment, as many as five macroblocks can be written or overwritten in a single write transaction.
    Type: Grant
    Filed: November 18, 2003
    Date of Patent: December 7, 2010
    Assignee: Broadcom Corporation
    Inventors: Lakshman Ramakrishnan, Sathish Kumar Radhakrishnan, Brian Schoner, Darren Neuman
  • Patent number: 7430680
    Abstract: A system and method use an aligning device to align clock signals of two logic devices before data transfer between them. In this example, the aligning device aligns a clock signal of a sequencer with a clock signal of a storage device before the sequencer transfers data to the storage device. The aligning device includes a phase detector that receives a first reference clock signal, which is used to control the storage device, and a delayed signal, which is used to control the sequencer, and generates a comparison clock signal. The comparison clock signal is filtered before being used to control a phase of a second reference clock signal, which is related to the first reference clock signal. The phase controlled second clock signal is an aligning clock signal that is feed back to a delay device to produce one or more subsequent delay device clock signals that are aligned to the storage device clock or first reference clock signal.
    Type: Grant
    Filed: June 29, 2005
    Date of Patent: September 30, 2008
    Assignee: Broadcom Corporation
    Inventors: Lionel J. D'Luna, Thomas A. Hughes, Sathish Kumar Radhakrishnan
  • Patent number: 7246341
    Abstract: Presented herein is a system and method for byte slice based DDR timing closure. In one embodiment, there is presented a method for synthesizing/laying out a dual data rate memory, said method comprising synthesizing/laying out a portion of the dual data rate memory; replicating the portion; and placing the synthesized/laid out portion and the replicated portions in proximity to a corresponding plurality of pads.
    Type: Grant
    Filed: August 13, 2004
    Date of Patent: July 17, 2007
    Assignee: Broadcom Corporation
    Inventors: Lionel D'Luna, Tom Hughes, Sathish Kumar Radhakrishnan
  • Patent number: 7111111
    Abstract: Methods of optimizing a plurality of numerically controlled delay lines (NCDLS) in a DDR memory controller are presented herein. In one embodiment, a method may comprise, for example, one or more of the following: acquiring a plurality of statistics, the plurality of statistics defining an operating region for the DDR memory controller; and calculating optimal values for the plurality of NCDLs, the optimal values calculated using the plurality of statistics.
    Type: Grant
    Filed: November 18, 2003
    Date of Patent: September 19, 2006
    Assignee: Broadcom Corporation
    Inventors: Darren Neuman, Sathish Kumar Radhakrishnan, Jeffrey Fisher, Joshua Stults, Nitin Borle, Kaushik Bhattacharya