Patents by Inventor Sathisha Nanjunde Gowda

Sathisha Nanjunde Gowda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Memory device with trimmable power gating capabilities
    Patent number: 8427886
    Abstract: A memory device includes at least one memory cell including a storage element electrically connected with a source potential line. A drive strength of the storage element is controlled as a function of a voltage level on the source potential line. The memory device further includes a clamp circuit electrically connected between the source potential line and a voltage source. The clamp circuit is operative to regulate the voltage level on the source potential line relative to the voltage source. A control circuit of the memory device is connected with the source potential line. The control circuit is operative to adjust the voltage level on the source potential line as a function of an operational mode of the memory device. A coarseness by which the voltage level on the source potential line is adjusted is selectively controlled as a function of at least a first control signal.
    Type: Grant
    Filed: July 11, 2011
    Date of Patent: April 23, 2013
    Assignee: LSI Corporation
    Inventors: Ankur Goel, Venkateswara Reddy Konudula, Sathisha Nanjunde Gowda
  • MEMORY DEVICE WITH TRIMMABLE POWER GATING CAPABILITIES
    Publication number: 20130016573
    Abstract: A memory device includes at least one memory cell including a storage element electrically connected with a source potential line. A drive strength of the storage element is controlled as a function of a voltage level on the source potential line. The memory device further includes a clamp circuit electrically connected between the source potential line and a voltage source. The clamp circuit is operative to regulate the voltage level on the source potential line relative to the voltage source. A control circuit of the memory device is connected with the source potential line. The control circuit is operative to adjust the voltage level on the source potential line as a function of an operational mode of the memory device. A coarseness by which the voltage level on the source potential line is adjusted is selectively controlled as a function of at least a first control signal.
    Type: Application
    Filed: July 11, 2011
    Publication date: January 17, 2013
    Applicant: LSI CORPORATION
    Inventors: Ankur Goel, Venkateswara Reddy Konudula, Sathisha Nanjunde Gowda