Abstract: By partitioning the source PHY of a physical layer interface, such as a DisplayPort interface, between multiple power domains, dynamic switching between various power modes with faster entry and exit latency can be achieved in some embodiments. In some embodiments, the scheme may be hardware initiated and autonomous in nature. A controller can switch the PHY in and out of the various power consumption modes, dependent on usage scenarios.

Abstract: By partitioning the source PHY of a physical layer interface, such as a DisplayPort interface, between multiple power domains, dynamic switching between various power modes with faster entry and exit latency can be achieved in some embodiments. In some embodiments, the scheme may be hardware initiated and autonomous in nature. A controller can switch the PHY in and out of the various power consumption modes, dependent on usage scenarios.

Abstract: A method for training the lanes of a main data link includes setting an initial lane voltage swing and conducting link at the initial value, and determining if link training was successful. If link training at the initial value of lane voltage swing was not successful, the value of lane voltage swing is incremented to a predetermined value. A determination is made as to whether the predetermined value of lane voltage swing exceeds a threshold value, and link training is ended if the predetermined value of lane voltage exceeds the threshold value. If the predetermined value of lane voltage swing does not exceed the threshold value, link training is conducted at the predetermined value of lane voltage swing until link training is successful or until a predetermined number of attempts at the predetermined value of lane voltage swing fail to successfully train the link.