Patents by Inventor Satinderjit Singh
Satinderjit Singh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11232833Abstract: A circuit includes a dummy wordline, a dummy bitline, and a dummy cell coupled to the dummy bitline. The dummy cell includes an active pulldown nMOSFET and a pass nMOSFET having a gate connected to the dummy wordline, a first source terminal connected to the drain terminal of the active pulldown nMOSFET, and a drain terminal connected to the dummy bitline. The circuit further includes a substrate-connected dummy bitline coupled to the source terminal of each active pulldown nMOSFET and coupled to a substrate.Type: GrantFiled: August 17, 2017Date of Patent: January 25, 2022Assignee: Arm LimitedInventors: Abhishek B. Akkur, Jitendra Dasani, Shri Sagar Dwivedi, Vivek Nautiyal, Satinderjit Singh, Vasimraja Bhavikatti
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Patent number: 10839861Abstract: Various implementations described herein are directed to an integrated circuit having multiple banks of memory cells and a local input/output (IO) component for each bank of the multiple banks. The integrated circuit may include multiple signal lines that are coupled to the multiple banks with the local IO components. At least one signal line of the multiple signal lines is wider than one or more of the other signal lines.Type: GrantFiled: January 26, 2018Date of Patent: November 17, 2020Assignee: Arm LimitedInventors: Vivek Nautiyal, Satinderjit Singh, Abhishek B. Akkur, Shri Sagar Dwivedi, Fakhruddin Ali Bohra, Jungtae Kwon, Jitendra Dasani, Manoj Puthan Purayil
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Publication number: 20190237111Abstract: Various implementations described herein are directed to an integrated circuit having multiple banks of memory cells and a local input/output (IO) component for each bank of the multiple banks. The integrated circuit may include multiple signal lines that are coupled to the multiple banks with the local IO components. At least one signal line of the multiple signal lines is wider than one or more of the other signal lines.Type: ApplicationFiled: January 26, 2018Publication date: August 1, 2019Inventors: Vivek Nautiyal, Satinderjit Singh, Abhishek B. Akkur, Shri Sagar Dwivedi, Fakhruddin Ali Bohra, Jungtae Kwon, Jitendra Dasani, Manoj Puthan Purayil
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Patent number: 10217496Abstract: Various implementations described herein are directed to an integrated circuit with memory circuitry having an array of bitcells that are accessible via multiple bitlines. The integrated circuit may include a write driver coupled to at least one bitline of the multiple bitlines through a column multiplexer. The integrated circuit may include a pass transistor coupled to the write driver and the column multiplexer via a write data line. The integrated circuit may include a charge storage device coupled between the pass transistor and write assist enable circuitry. The integrated circuit may include a transmission gate coupled to a gate of the write driver. The integrated circuit may include a clamp transistor coupled between the gate of write driver and the charge storage device such that the clamp transistor receives a voltage assist signal from the charge storage device at the gate of the write driver.Type: GrantFiled: February 28, 2018Date of Patent: February 26, 2019Assignee: ARM LimitedInventors: Vivek Nautiyal, Jitendra Dasani, Satinderjit Singh, Shri Sagar Dwivedi, Bo Zheng, Fakhruddin Ali Bohra
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Publication number: 20190057735Abstract: A circuit includes a dummy wordline, a dummy bitline, and a dummy cell coupled to the dummy bitline. The dummy cell includes an active pulldown nMOSFET and a pass nMOSFET having a gate connected to the dummy wordline, a first source terminal connected to the drain terminal of the active pulldown nMOSFET, and a drain terminal connected to the dummy bitline. The circuit further includes a substrate-connected dummy bitline coupled to the source terminal of each active pulldown nMOSFET and coupled to a substrate.Type: ApplicationFiled: August 17, 2017Publication date: February 21, 2019Inventors: Abhishek B. Akkur, Jitendra Dasani, Shri Sagar Dwivedi, Vivek Nautiyal, Satinderjit Singh, Vasimraja Bhavikatti
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Patent number: 10140399Abstract: Various implementations described herein are directed to a computing device. The computing device may include a mapper module that receives a user configuration input of a destination corner for building a destination corner database. The mapper module may include a decision making engine that decides fabrication parameters for building the destination corner database based on the verified user configuration input and memory compiler metadata. The computing device may include a builder module that performs a simulation of the destination corner based on the fabrication parameters, collects simulation results data associated with the simulation, and builds the destination corner database for the destination corner based on the simulation results data and source corner data.Type: GrantFiled: December 21, 2016Date of Patent: November 27, 2018Assignee: ARM LimitedInventors: Hongwei Zhu, Mouli Rajaram Chollangi, Hemant Joshi, Yew Keong Chong, Satinderjit Singh, Betsie Jacob, Neeraj Dogra, Sriram Thyagarajan
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Patent number: 10074410Abstract: Various implementations described herein may refer to and may be directed to an integrated circuit using shaping and timing circuitries. In one implementation, an integrated circuit may include memory that is accessed based on a voltage level on a first control line, and may include a control driver circuitry coupled to the first and a second control line that drives a first and a second control signal toward first or second voltage levels. The integrated circuit may include a shaper circuitry coupled to the control lines that includes a first clamping transistor that couples the first control line to a timed supply node in response to the driving of the second control signal toward the first voltage. The integrated circuit may include a timing circuitry coupled to the first shaper circuitry that includes a header transistor that couples the timed supply node to a voltage supply source.Type: GrantFiled: September 30, 2016Date of Patent: September 11, 2018Assignee: ARM LimitedInventors: Vivek Nautiyal, Jitendra Dasani, Fakhruddin Ali Bohra, Satinderjit Singh, Shri Sagar Dwivedi
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Publication number: 20180173822Abstract: Various implementations described herein are directed to a computing device. The computing device may include a mapper module that receives a user configuration input of a destination corner for building a destination corner database. The mapper module may include a decision making engine that decides fabrication parameters for building the destination corner database based on the verified user configuration input and memory compiler metadata. The computing device may include a builder module that performs a simulation of the destination corner based on the fabrication parameters, collects simulation results data associated with the simulation, and builds the destination corner database for the destination corner based on the simulation results data and source corner data.Type: ApplicationFiled: December 21, 2016Publication date: June 21, 2018Inventors: Hongwei Zhu, Mouli Rajaram Chollangi, Hemant Joshi, Yew Keong Chong, Satinderjit Singh, Betsie Jacob, Neeraj Dogra, Sriram Thyagarajan
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Publication number: 20180096715Abstract: Various implementations described herein may refer to and may be directed to an integrated circuit using shaping and timing circuitries. In one implementation, an integrated circuit may include memory that is accessed based on a voltage level on a first control line, and may include a control driver circuitry coupled to the first and a second control line that drives a first and a second control signal toward first or second voltage levels. The integrated circuit may include a shaper circuitry coupled to the control lines that includes a first clamping transistor that couples the first control line to a timed supply node in response to the driving of the second control signal toward the first voltage. The integrated circuit may include a timing circuitry coupled to the first shaper circuitry that includes a header transistor that couples the timed supply node to a voltage supply source.Type: ApplicationFiled: September 30, 2016Publication date: April 5, 2018Inventors: Vivek Nautiyal, Jitendra Dasani, Fakhruddin Ali Bohra, Satinderjit Singh, Shri Sagar Dwivedi
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Patent number: 9911510Abstract: Various implementations described herein are directed to an integrated circuit having a memory cell array with multiple rows of memory cells including at least one redundant row of memory cells. The memory cell array may be partitioned into multiple regions of memory cells including a first region of memory cells corresponding to a first part of the redundant row of memory cells and a second region of memory cells corresponding to a second part of the redundant row of memory cells. The integrated circuit may include wordline driver circuitry coupled to the first and second regions of memory cells and their corresponding first and second parts of the redundant row of memory cells. In some instances, the integrated circuit may include row shift circuitry coupled to the first and second regions of memory cells and their corresponding first and second parts of the redundant row of memory cells.Type: GrantFiled: October 7, 2016Date of Patent: March 6, 2018Assignee: ARM LimitedInventors: Jungtae Kwon, Young Suk Kim, Vivek Nautiyal, Pranay Prabhat, Fakhruddin Ali Bohra, Shri Sagar Dwivedi, Satinderjit Singh, Lalit Gupta
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Patent number: 9824749Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include precharge circuitry for precharging bitlines to a source voltage level. The integrated circuit may include write assist circuitry having a charge storage element for providing a write assist signal to at least one of the bitlines. The integrated circuit may include read assist circuitry having a switching element for providing charge sharing between the bitlines, the precharge circuitry, and the charge storage element of the write assist circuitry.Type: GrantFiled: September 2, 2016Date of Patent: November 21, 2017Assignee: ARM LimitedInventors: Vivek Nautiyal, Fakhruddin Ali Bohra, Satinderjit Singh, Shri Sagar Dwivedi, Abhishek B. Akkur
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Patent number: 9711243Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include a first memory cell array disposed in a first area of the integrated circuit. The first memory cell array includes first memory cells. The integrated circuit may include a second memory cell array disposed in a second area of the integrated circuit that is different than the first area. The second memory cell array includes redundant memory cells that are separate from the first memory cells.Type: GrantFiled: June 21, 2016Date of Patent: July 18, 2017Assignee: ARM LimitedInventors: Vivek Nautiyal, Fakhruddin Ali Bohra, Satinderjit Singh, Jitendra Dasani, Shri Sagar Dwivedi