Abstract: In some aspects, the present disclosure provides a method for managing a command queue in a universal flash storage (UFS) host device. The method includes determining to power on a first subsystem of a system-on-a-chip (SoC), wherein the determination to power on the first subsystem is made by a second subsystem of the SoC based on detection of user identity data contained in a first image frame during an initial biometric detection process. In certain aspects, the second subsystem is configured to operate independent of the first subsystem and control power to the first subsystem. In certain aspects, the second subsystem includes a second optical sensor, a set of ambient sensors, and a second processor configured to detect, via a set of ambient sensors, an event comprising one or more of an environmental event outside of the device or a motion event of the device.

Abstract: In illustrative examples described herein, a hardware-based mechanism is provided to prevent brute force attacks on user credentials. In some examples, a throttling policy is added to a hardware key manager to provide timer-based throttling using a secure hardware timer. A register or slot in hardware is used to maintain throttling policy attributes or parameters for tracking a throttle count and a timeout value to be enforced. During a cryptographic wrap operation, a user key is associated with, or bound to, the slot or register. During a subsequent unwrap operation, the hardware key manager then enforces any needed timeouts by throttling user access in response to any incorrect entries based on the throttling policy attributes or parameters maintained in the slot or register. Examples exploiting an always-on battery-backed processing island are also provided. In some examples, throttling is implemented without the use of any secure storage.

Abstract: Various embodiments provide for correcting pre-cursor intersymbol interference (ISI) and post-cursor ISI in a data signal received over a channel. More particularly, some embodiments correct pre-cursor ISI and post-cursor ISI using decision feedback equalization (DFE).

Abstract: Techniques for providing data protection in an integrated circuit are provided. A method according to these techniques includes exchanging messages with an off-chip, non-volatile memory to securely initialize an anti-replay counter (ARC) value in the integrated circuit based on an ARC value stored in the off-chip, non-volatile memory, and maintaining the ARC value stored in the integrated circuit such that the ARC value stored in the integrated circuit remains synchronized with the ARC value stored in the off-chip, non-volatile memory.

Abstract: Techniques for providing countermeasures against physical attacks on the contents of off-chip memory are provided in which a pseudo-internal memory resistant to physical attack is used. The pseudo-internal memory is mapped to an address space such that the pseudo-internal memory appears to be on-chip memory to a processor or a system on a chip (SoC). A method for protecting sensitive data according to these techniques includes presenting, by a pseudo-internal memory module of a SoC, an address space as internal memory of the SoC, where the address space comprises memory located off-chip from the system on a chip, receiving a data write request at the pseudo-internal memory module from a component of the SoC, encrypting data associated with the data write request using the pseudo-internal memory module to generate encrypted data, and writing the encrypted data to the memory located off-chip from the SoC.

Abstract: A packet processing system is embodied on an ASIC is optimized for processing IPSec security protocol packets in a hardware configuration. Embedded RISC processors operate with hardware support modules providing for IPSec packet processing at OC24 data rates and greater. IPSec packets are received through a streaming interface and buffered in an external memory. When the entire packet is in external memory, portions are buffered in a local memory for crypto-processing. As portions of the packets complete processing, the portions are buffered to an output portion of the external memory associated with the channel. When an entire packet competes processing, portions are buffered to a local memory for streaming. The hardware accordingly reduces the involvement of the RISC processors and significantly increases channel throughput providing for high-speed IPSec packet processing.

Abstract: An encryption processing system implements an encryption algorithm using a memory system comprising a multiple-port memory by performing at least one set of parallel read and write operations to the memory. The algorithm is, for example, the conventional ARCFOUR (or RC4) algorithm, and the key and state array used in the ARCFOUR algorithm are stored in the multiple port memory. During execution of the ARCFOUR algorithm, a read from one port of the multiple port memory of a state array value is done while another port is used to write a new value to the state array. The use of such parallel read and write operations uses a comparator system that determines whether to use certain previously-read values from the state array or to read a new value from the state array when selecting the pseudorandom K byte to calculate the output data byte.

Abstract: A packet processing system is embodied on an ASIC is optimized for processing IPSec security protocol packets in a hardware configuration. Embedded RISC processors operate with hardware support modules providing for IPSec packet processing at OC24 data rates and greater. IPSec packets are received through a streaming interface and buffered in an external memory. When the entire packet is in external memory, portions are buffered in a local memory for crypto-processing. As portions of the packets complete processing, the portions are buffered to an output portion of the external memory associated with the channel. When an entire packet competes processing, portions are buffered to a local memory for streaming. The hardware accordingly reduces the involvement of the RISC processors and significantly increases channel throughput providing for high-speed IPSec packet processing.

Abstract: An encryption processing system implements an encryption algorithm using a memory system comprising a multiple-port memory by performing at least one set of parallel read and write operations to the memory. The algorithm is, for example, the conventional ARCFOUR (or RC4) algorithm, and the key and state array used in the ARCFOUR algorithm are stored in the multiple port memory. During execution of the ARCFOUR algorithm, a read from one port of the multiple port memory of a state array value is done while another port is used to write a new value to the state array. The use of such parallel read and write operations uses a comparator system that determines whether to use certain previously-read values from the state array or to read a new value from the state array when selecting the pseudorandom K byte to calculate the output data byte.

Abstract: Crystallizable liquid solutions (i.e. solutions with crystallizable solvents) are concentrated by passing them between two cooled surfaces in a direction transverse to the action of gravity, the crystals being removed from the liquid substantially continuously over the entire length of the path. The surfaces are vibrated to prevent accumulation of crystals.