Abstract: Multiple classifier models are applied to features of a circuit design after processing the design through a first phase of an implementation flow. Each classifier model is associated with one of multiple directives, the directives are associated with a second phase of the implementation flow, and each classifier model returns a value indicative of likelihood of improving a quality metric. Regressor models of each set of a plurality of sets of regressor models are applied to the features. Each directive is associated with one of the sets of regressor models, and a combined score from each set of regressor models indicates a likelihood of satisfying a constraint. The directives are ranked based on the values indicated by the classifier models and scores from the sets of regressor models, and the circuit design is processed n the second phase of the implementation flow by the design tool using the directive having the highest rank.

Abstract: Disclosed approaches for guiding actions in processing a circuit design include a design tool identifying first violations of design checks and determining severity levels of the first violations. The design tool determines for each violation, suggested actions associated with the violation and presents on a display, first data indicative of the suggested actions in order of the severity levels of the first violations. The first data include selectable objects, and each selectable object has an associated executable procedure. The design tool can execute the procedure associated with one of the selectable objects in response to selection and modify the circuit design in response to execution of the procedure.

Abstract: There is provided a system for generating configuration data for implementing a circuit design in a segmented reconfigurable device. A placement and routing design aiding system (30) includes a database (31) for storing hardware information (89) including data of PEs included in each segment and data of a first-level and second-level routing matrix and an apparatus (33) for mapping the circuit design onto the PEs. The mapping apparatus (33) generates mappings of the circuit design onto the PEs by carrying out an iterative algorithm that minimizes a cost function based on the hardware information (89). The cost function includes an item that minimizes usage of the second-level routing matrix (22) that connects between the segments.

Abstract: There is provided a system for generating configuration data for implementing a circuit design in a segmented reconfigurable device. A placement and routing design aiding system (30) includes a database (31) for storing hardware information (89) including data of PEs included in each segment and data of a first-level and second-level routing matrix and an apparatus (33) for mapping the circuit design onto the PEs. The mapping apparatus (33) generates mappings of the circuit design onto the PEs by carrying out an iterative algorithm that minimizes a cost function based on the hardware information (89). The cost function includes an item that minimizes usage of the second-level routing matrix (22) that connects between the segments.