Abstract: An apparatus comprising a pullup circuit, a pulldown circuit, and a control circuit. The pullup circuit may be configured to receive a first and second control signal. The pulldown circuit may be configured to receive a third and fourth control signal. The control circuit may be configured to generate the first, second, third and fourth control signals. The control circuit may comprise (i) a first and second control device coupled between the first and second control signals and a supply and (ii) a third and fourth control device coupled between the third and fourth control signals and the supply.

Abstract: An apparatus comprising a first device and a second device. The first device may be connected to a first supply voltage. The second device may be connected (i) in series with the first device and (ii) to a second supply voltage. The first device is generally biased to provide enhanced noise suppression performance. The second device is generally configured to switch between the first and second supply voltages.

Abstract: An apparatus comprising a first circuit, a second circuit and a switch. The first circuit may be configured to receive a first supply voltage and may be coupled to a first ground. The second circuit may be configured to receive a second supply voltage and may be coupled to a second ground. The second circuit may be disabled in response to a control signal. The first and second supply voltages may be controlled by a reference voltage. The switch may be coupled between the first and second circuits and may be configured to connect the first and second circuits when the second circuit is disabled.

Abstract: A circuit and method comprising a memory, a first latch, a second latch and a control circuit. The memory may be configured to write information in response to (i) an input data signal and (ii) an address signal. The first latch may be configured to hold the address in response to a control signal. The second latch may be configured to hold the data input signal in response to the control signal. The control circuit may be configured to present the control signal in response to (i) an enable signal and (ii) a detect signal.

Abstract: A circuit and method for generating an evaluation signal used to turn OFF one or more sense amplifiers. The sense amplifiers may be configured to present a first and second output in response to (i) an input signal and (ii) an enable signal. A detect circuit may be configured to present a detect signal in response to the first and second outputs. A control circuit may be configured to present the enable signal in response to (i) the detect signal and (ii) a wordline signal.

Abstract: A circuit and method comprising a memory, a first latch, a second latch and a control circuit. The memory may be configured to write information in response to (i) an input data signal and (ii) an address signal. The first latch may be configured to hold the address in response to a control signal. The second latch may be configured to hold the data input signal in response to the control signal. The control circuit may be configured to present the control signal in response to (i) a detect signal and (ii) a transition of the address signal.

Abstract: A circuit comprising a sense amplifier, an evaluation circuit, a control circuit and a register circuit. The sense amplifier circuit may be configured to present a first output and a second output in response to (i) an input signal and (ii) an enable signal. The evaluation circuit may be configured to present an evaluation signal in response to the first and second outputs. The control circuit may be configured to present (i) a first clock signal, a second clock signal and an enable signal in response to (i) the evaluation signal and (ii) a wordline signal. The register circuit may be configured to hold either the first or second output in response to the first and second clock signals. The register circuit may be implemented as a master-slave register that may respond to the first and second clock signals.

Abstract: The present invention concerns a circuit comprising a memory array having a plurality of wordlines and a plurality of bitlines, a reference circuit, a column select circuit, an enable control circuit, and one or more sense amplifiers. The reference circuit may be configured to present a reference voltage signal in response to (i) a dummy wordline and (ii) a virtual ground signal, where the dummy wordline may be synchronized with each of the plurality of wordlines. The column select circuit may be configured to present the virtual ground signal in response to a column select signal. The enable control circuit may be configured to present an enable signal in response to the dummy wordline. The sense amplifiers may be configured to generate an output in response to (i) the enable signal, (ii) the reference signal and (iii) the bitlines.

Abstract: The present invention concerns a method and apparatus for providing a dual level wordline clamp for use in a memory array. During a write operation, the clamp is at a level that ensures that a proper write margin is maintained. During a read operation, the clamp produces a lower level that reduces the overall current consumption of the circuit. During a write operation, the clamp also reduces the overall current consumption of the circuit. The present invention does not require complex reference circuits and, as a result, presents a minimal impact on die size.

Abstract: The present invention concerns a method and apparatus for providing a dual level wordline clamp for use in a memory array. During a write operation, the clamp is at a level that ensures that a proper write margin is maintained. During a read operation, the clamp produces a lower level that reduces the overall current consumption of the circuit. During a write operation, the clamp also reduces the overall current consumption of the circuit. The present invention does not require complex reference circuits and, as a result, presents a minimal impact on die size.

Abstract: A level shifting circuit includes first and second load, gain and reference transistors. The first and second load transistors each have a source-drain path arranged between Vdd and Vss power supply voltages, and a gate coupled to the Vss power supply voltage. The first and second gain transistors each have a source-drain path arranged between the respective source-drain paths of the first and second load transistors and the Vss power supply voltage, and gates serving as respective differential input nodes. The first and second reference transistors each have a source-drain path arranged between the Vdd and Vss power supply voltages, and a gate coupled to respective first and second nodes serving as respective differential output nodes, the first node connecting the source-drain path of the first load transistor with the source-drain path of the first gain transistor, and the second node connecting the source-drain path of the second load transistor with the source-drain path of the second gain transistor.

Abstract: The present invention concerns a circuit and method for disabling the load transistors from the bitlines of a memory array without requiring a fuse. After a particular column is disabled in a redundant memory array system, a short between the particular bitline and ground is detected by a control circuit that shuts off the appropriate bitline load. The disconnecting of the particular bitline load does not affect any of the normal read or write operations of the circuit. The present invention detects whether the short exists and provides the disabling feature while maintaining the ability to distinguish between a normal write condition and a condition that resembles a bitline short. After a write occurs, the bitline load will remain active. The ability of the present invention to distinguish between a normal write and a bitline short allows for transparent operation.

Abstract: The present invention concerns a method and apparatus that generally prevents an output glitch in a sense amplifier during a transition from a strong zero to a weak zero. When multiple cells are turned on, a virtual ground node is raised high due to the current flowing through the virtual ground device. A recover node is generally held close to the read product term line RPT. When a transition from a strong zero occurs, the recover node swings to VCC and provides conductance on the virtual ground node which generally eliminates the glitch.

Abstract: The present invention concerns a method and apparatus that generally prevents a glitch from occurring in an output of a sense amplifier during a transition from a strong zero to a weak zero. The present invention detects the voltage difference between a virtual ground node and a read product term line and turns off a pull down of a first stage of the sense amplifier. The low on the read product term line generally causes a node between the first and second stage of the sense amplifier to swing high for both a strong or weak zero condition. A diode clamp generally limits the current drawn under the strong or weak zero condition by clamping the output of the first stage from going too high. When a transition from a strong zero to a weak zero occurs, the output of the first stage essentially remains high since the gate to source drive on the pulldown remains considerably weak.