Patents by Inventor Satish D. Athavale
Satish D. Athavale has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6670233Abstract: A process for forming a multilayer film stack including a noble metal electrode and a multilayer barrier. The process includes exposing the film stack to a plasma formed of reactive species from an excitable gas mixture of argon, a chlorine bearing gas, a fluorine bearing gas and a carbon bearing gas. The method of forming the lower electrode of a capacitor includes simultaneously etching a multilayer barrier and an electrode layer.Type: GrantFiled: February 4, 2003Date of Patent: December 30, 2003Assignee: International Business Machines CorporationInventors: Satish D. Athavale, Greg Costrini
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Publication number: 20030143803Abstract: A process for forming a multilayer film stack including a noble metal electrode and a multilayer barrier. The process includes exposing the film stack to a plasma formed of reactive species from an excitable gas mixture of argon, a chlorine bearing gas, a fluorine bearing gas and a carbon bearing gas. The method of forming the lower electrode of a capacitor includes simultaneously etching a multilayer barrier and an electrode layer.Type: ApplicationFiled: February 4, 2003Publication date: July 31, 2003Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Satish D. Athavale, Greg Costrini
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Patent number: 6559001Abstract: A process for forming a multilayer film stack including a noble metal electrode and a multilayer barrier. The process includes exposing the film stack to a plasma formed of reactive species from an excitable gas mixture of argon, a chlorine bearing gas, a fluorine bearing gas and a carbon bearing gas. The method of forming the lower electrode of a capacitor includes simultaneously etching a multilayer barrier and an electrode layer.Type: GrantFiled: May 30, 2001Date of Patent: May 6, 2003Assignee: International Business Machines CorporationInventors: Satish D. Athavale, Greg Costrini
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Patent number: 6548414Abstract: A method for etching material which does not readily form volatile compounds in a plasma includes providing a plasma etch chamber including a wafer electrode at an initial temperature. The wafer electrode supports a wafer, and the wafer includes a layer of the material which does not readily form volatile compounds in plasma. The wafer is bombarded with charged particles from a plasma generated in the plasma etch chamber to impart thermal energy to the wafer. A reactive gas flow is provided to react with etch products of the material. Bias power is applied to the wafer electrode to impart bombardment energy to the charged particles incident on the wafer from the plasma such that a predetermined temperature is generated on a surface of the wafer wherein the wafer electrode is maintained at about the initial temperature.Type: GrantFiled: September 14, 1999Date of Patent: April 15, 2003Assignees: Infineon Technologies AG, International Business Machines Corp.Inventors: Satish D. Athavale, Martin Gutsche
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Patent number: 6518118Abstract: Semiconductor devices generally, and in particular DRAM memory devices, having buried, single-sided conductors are provided. Additionally, methods of fabricating semiconductor devices having buried, single-sided conductors are provided.Type: GrantFiled: March 15, 2001Date of Patent: February 11, 2003Assignee: International Business Machines CorporationInventors: Satish D. Athavale, Ramachandra Divakaruni, Jack A. Mandelman
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Publication number: 20020192900Abstract: A process for forming a multilayer film stack including a noble metal electrode and a multilayer barrier. The process includes exposing the film stack to a plasma formed of reactive species from an excitable gas mixture of argon, a chlorine bearing gas, a fluorine bearing gas and a carbon bearing gas. The method of forming the lower electrode of a capacitor includes simultaneously etching a multilayer barrier and an electrode layer.Type: ApplicationFiled: May 30, 2001Publication date: December 19, 2002Applicant: International Business Machines CorporationInventors: Satish D. Athavale, Greg Costrini
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Publication number: 20020130346Abstract: Semiconductor devices generally, and in particular DRAM memory devices, having buried, single-sided conductors are provided. Additionally, methods of fabricating semiconductor devices having buried, single-sided conductors are provided.Type: ApplicationFiled: March 15, 2001Publication date: September 19, 2002Applicant: International Business Machines CorporationInventors: Satish D. Athavale, Ramachandra Divakaruni, Jack A. Mandelman
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Patent number: 6420272Abstract: In semiconductor dynamic random access memory circuits using stacked capacitor storage elements formed using high permittivity dielectric material, it is typical to form the stacked capacitors using noble metal electrodes. Typically, the etching process for the noble metal electrodes requires the use of a hard mask patterning material such as silicon oxide. Removal of this hard mask frequently results in damage to the dielectric surface surrounding the patterned noble metal electrode.Type: GrantFiled: December 14, 1999Date of Patent: July 16, 2002Assignees: Infineon Technologies A G, International Business Machines CorporationInventors: Hua Shen, David Edward Kotecki, Satish D. Athavale, Jenny Lian, Gerhard Kunkel, Nimal Chaudhary
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Patent number: 6420099Abstract: A method for patterning an aluminum-containing layer. A tungsten-containing layer is provided over an aluminum-containing layer. The tungsten-containing layer is patterned to form an opening therein, so that the opening exposes an underlying portion of the aluminum-containing layer. The patterned tungsten-containing layer is exposed to an etch having a substantially higher etch rate of the aluminum-containing layer than of the tungsten-containing layer to remove the exposed portion of the aluminum-containing layer.Type: GrantFiled: August 2, 1999Date of Patent: July 16, 2002Assignees: Infineon Technologies AG, International Business Machines CorporationInventors: Martin Gutsche, Satish D. Athavale
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Method and apparatus for minimizing semiconductor wafer arcing during semiconductor wafer processing
Patent number: 6406925Abstract: A method and apparatus for minimizing or eliminating arcing or dielectric breakdown across a wafer during a semiconductor wafer processing step includes controlling the voltage across the wafer so that arcing and/or dielectric breakdown does not occur. Using an electrostatic clamp of the invention and by controlling the specific clamp voltage to within a suitable range of values, the voltage across a wafer is kept below a threshold and thus, arcing and/or dielectric breakdown is reduced or eliminated.Type: GrantFiled: November 14, 2000Date of Patent: June 18, 2002Assignee: Tegal CorporationInventors: Satish D. Athavale, Leslie G. Jerde, John A. Meyer -
Patent number: 6348374Abstract: A method of forming a vertical transistor. A pad layer is formed over a semiconductor substrate. A trough is formed through the pad layer and in the semiconductor substrate. A bit line is formed buried in the trough. The bit line is enclosed by a dielectric material. A strap is formed extending through the dielectric material to connect the bit line to the semiconductor substrate. The trough is filled above the bit line with a conductor. The conductor is cut along its longitudinal axis such that the conductor remains on one side of the trough. Wordline troughs are formed, substantially orthogonal to the bit line, above the semiconductor substrate. A portion of the conductor is removed under the wordline trough to separate the conductor into separate gate conductors. Wordlines are formed in the wordline trough connected to the separate gate conductors.Type: GrantFiled: June 19, 2000Date of Patent: February 19, 2002Assignee: International Business MachinesInventors: Satish D. Athavale, Gary B. Bronner, Ramachandra Divakaruni, Ulrike Gruening, Jack A. Mandelman, Carl J. Radens
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Method and apparatus for minimizing semiconductor wafer arcing during semiconductor wafer processing
Patent number: 6346428Abstract: A method and apparatus for minimizing or eliminating arcing or dielectric breakdown across a wafer during a semiconductor wafer processing step includes controlling the voltage across the wafer so that arcing and/or dielectric breakdown does not occur. Using an electrostatic clamp of the invention and by controlling the specific clamp voltage to within a suitable range of values, the voltage across a wafer is kept below a threshold and thus, arcing and/or dielectric breakdown is reduced or eliminated.Type: GrantFiled: August 17, 1998Date of Patent: February 12, 2002Assignee: Tegal CorporationInventors: Satish D. Athavale, Leslie G. Jerde, John A. Meyer -
Publication number: 20010053610Abstract: A method for etching material which does not readily form volatile compounds in a plasma includes providing a plasma etch chamber including a wafer electrode at an initial temperature. The wafer electrode supports a wafer, and the wafer includes a layer of the material which does not readily form volatile compounds in plasma. The wafer is bombarded with charged particles from a plasma generated in the plasma etch chamber to impart thermal energy to the wafer. A reactive gas flow is provided to react with etch products of the material. Bias power is applied to the wafer electrode to impart bombardment energy to the charged particles incident on the wafer from the plasma such that a predetermined temperature is generated on a surface of the wafer wherein the wafer electrode is maintained at about the initial temperature.Type: ApplicationFiled: September 14, 1999Publication date: December 20, 2001Inventors: SATISH D. ATHAVALE, MARTIN GUTSCHE
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Patent number: 6261967Abstract: A method for forming a patterned shape from a noble metal, in accordance with the present invention, includes forming a noble metal layer over a dielectric layer and patterning a hard mask layer on the noble metal layer. The hard mask layer includes a mask material that is selectively removable relative to the noble metal layer and the dielectric layer and capable of withstanding plasma etching. Alternately, the hard mask material may be consumable during the noble metal layer plasma etching. Plasma etching is performed on the noble metal layer in accordance with the patterned hard mask layer. The hard mask layer is removed such that a patterned shape formed in the noble metal layer remains intact after the plasma etching and the hard mask removal.Type: GrantFiled: February 9, 2000Date of Patent: July 17, 2001Assignees: Infineon Technologies North America Corp., International Business Machine CorporationInventors: Satish D. Athavale, Hua Shen, David Kotecki, Jenny Lian
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Patent number: 6207584Abstract: A method for forming a dielectric layer includes exposing a surface to a first dielectric material in gaseous form at a first temperature. Nuclei of the first dielectric material are formed on the surface. A layer of a second dielectric material is deposited on the surface by employing the nuclei as seeds for layer growth wherein the depositing is performed at a second temperature which is greater than the first temperature.Type: GrantFiled: January 5, 2000Date of Patent: March 27, 2001Assignees: International Business Machines Corp., Infineon Technologies North America Corp.Inventors: Hua Shen, David E. Kotecki, Robert Laibowitz, Katherine Lynn Saenger, Satish D. Athavale, Jenny Lian, Martin Gutsche, Yun-Yu Wang, Thomas Shaw