Abstract: Techniques are described herein to enhance capability of floating level translators. For example, increased headroom is accomplished by adaptively bypassing the protection elements of the voltage level translator. In an example, a floating level translator can translate an input signal from a low-voltage domain to a high-voltage domain. A bypass circuit is coupled across the protection elements. The bypass circuit selectively engages during low-voltage operation (e.g., thereby providing a lower loss path relative to loss caused by the high-voltage protection elements and thus increasing the headroom swing), and disengages responsive to the high-voltage reference rail of the high-voltage domain exceeding a threshold or otherwise being high enough (e.g., greater than the potential of the low-voltage domain power rail). The bypass circuit can be implemented in a relatively low-complexity manner (e.g., back-to-back high-voltage FETs) without additional signals to control low-voltage capability.

Abstract: Techniques are described herein to enhance capability of floating level translators. For example, increased headroom is accomplished by adaptively bypassing the protection elements of the voltage level translator. In an example, a floating level translator can translate an input signal from a low-voltage domain to a high-voltage domain. A bypass circuit is coupled across the protection elements. The bypass circuit selectively engages during low-voltage operation (e.g., thereby providing a lower loss path relative to loss caused by the high-voltage protection elements and thus increasing the headroom swing), and disengages responsive to the high-voltage reference rail of the high-voltage domain exceeding a threshold or otherwise being high enough (e.g., greater than the potential of the low-voltage domain power rail). The bypass circuit can be implemented in a relatively low-complexity manner (e.g., back-to-back high-voltage FETs) without additional signals to control low-voltage capability.

Abstract: Techniques are described herein to enhance capability of floating level translators. For example, increased headroom is accomplished by adaptively bypassing the protection elements of the voltage level translator. In an example, a floating level translator can translate an input signal from a low-voltage domain to a high-voltage domain. A bypass circuit is coupled across the protection elements. The bypass circuit selectively engages during low-voltage operation (e.g., thereby providing a lower loss path relative to loss caused by the high-voltage protection elements and thus increasing the headroom swing), and disengages responsive to the high-voltage reference rail of the high-voltage domain exceeding a threshold or otherwise being high enough (e.g., greater than the potential of the low-voltage domain power rail). The bypass circuit can be implemented in a relatively low-complexity manner (e.g., back-to-back high-voltage FETs) without additional signals to control low-voltage capability.

Abstract: Disclosed examples include flyback converters, control circuits and methods to facilitate secondary side regulation of the output voltage. A primary side control circuit operates a primary side switch to independently initiate power transfer cycles to deliver power to a transformer secondary winding in a first mode. A secondary side control circuit operates a synchronous rectifier or secondary side switch to generate a predetermined cycle start request signal via a transformer auxiliary winding to assume secondary side regulation and to cause the primary side controller to initiate new power transfer cycles.

Abstract: In some examples, a circuit includes a capacitor having a first terminal and a second terminal, the first terminal coupled to a voltage supply terminal of the circuit. The circuit also includes a transistor having a transistor gate, a transistor drain, and a transistor source, the transistor source coupled to ground and the transistor drain coupled to an input terminal of the circuit. The transistor is configured to conduct responsive to a gate signal received at the transistor gate, the gate signal based on a signal provided at the second terminal of the capacitor. The circuit also includes a Schmitt trigger having a Schmitt trigger input coupled to the transistor drain.

Abstract: Disclosed examples include flyback converters, control circuits and methods to facilitate secondary side regulation of the output voltage. A primary side control circuit operates a primary side switch to independently initiate power transfer cycles to deliver power to a transformer secondary winding in a first mode. A secondary side control circuit operates a synchronous rectifier or secondary side switch to generate a predetermined cycle start request signal via a transformer auxiliary winding to assume secondary side regulation and to cause the primary side controller to initiate new power transfer cycles.

Abstract: An apparatus includes a differential input pair, a first resistor, a second resistor, and a comparator. The differential input pair having first and second differential inputs. The first differential input is adapted to be coupled to an output of a controller and the second differential input is adapted to be coupled to a signal ground of the controller. The first resistor is adapted to be coupled to a third resistor via the first differential input to form a first voltage divider. The second resistor is adapted to be coupled to a fourth resistor via the second differential input to form a second voltage divider. The comparator having first and second comparator inputs. The first comparator input is coupled between the first resistor and the first differential input. The second comparator input is coupled between the second resistor and the second differential input.

Abstract: Gate driver bootstrap circuits and related methods are disclosed. An example gate driver stage includes a first terminal and a second terminal, the first terminal to be coupled to a capacitor, the capacitor and the second terminal to be coupled to a gate terminal of a power transistor, a gate driver coupled to the first terminal and the second terminal, and a bootstrap circuit coupled to the first terminal, the second terminal, and the gate driver, the bootstrap circuit including a control stage circuit having an output and a first transistor having a first gate terminal and a first current terminal, the first gate terminal coupled to the output, the first current terminal coupled to the first terminal.

Abstract: An apparatus includes a differential input pair, a first resistor, a second resistor, and a comparator. The differential input pair having first and second differential inputs. The first differential input is adapted to be coupled to an output of a controller and the second differential input is adapted to be coupled to a signal ground of the controller. The first resistor is adapted to be coupled to a third resistor via the first differential input to form a first voltage divider. The second resistor is adapted to be coupled to a fourth resistor via the second differential input to form a second voltage divider. The comparator having first and second comparator inputs. The first comparator input is coupled between the first resistor and the first differential input. The second comparator input is coupled between the second resistor and the second differential input.

Abstract: Gate driver bootstrap circuits and related methods are disclosed. An example gate driver stage includes a first terminal and a second terminal, the first terminal to be coupled to a capacitor, the capacitor and the second terminal to be coupled to a gate terminal of a power transistor, a gate driver coupled to the first terminal and the second terminal, and a bootstrap circuit coupled to the first terminal, the second terminal, and the gate driver, the bootstrap circuit including a control stage circuit having an output and a first transistor having a first gate terminal and a first current terminal, the first gate terminal coupled to the output, the first current terminal coupled to the first terminal.

Abstract: Methods, systems, and apparatus to increase common-mode transient immunity in isolation devices is disclosed. An example apparatus includes a current mirror including an input terminal and an output terminal; a transistor including a gate terminal, a first current terminal, and a second current terminal, the gate terminal coupled to a reference voltage terminal, the first current terminal coupled to the input terminal of the current mirror, and the second current terminal coupled to an input node; a buffer including an input terminal and an output terminal, the input terminal of the buffer coupled to the output terminal of the current mirror; and a logic gate including an input terminal and an output terminal, the input terminal of the logic gate coupled to the output terminal of the buffer.

Abstract: Methods, systems, and apparatus to increase common-mode transient immunity in isolation devices is disclosed. An example apparatus includes a current mirror including an input terminal and an output terminal; a transistor including a gate terminal, a first current terminal, and a second current terminal, the gate terminal coupled to a reference voltage terminal, the first current terminal coupled to the input terminal of the current mirror, and the second current terminal coupled to an input node; a buffer including an input terminal and an output terminal, the input terminal of the buffer coupled to the output terminal of the current mirror; and a logic gate including an input terminal and an output terminal, the input terminal of the logic gate coupled to the output terminal of the buffer.

Abstract: Methods, systems, and apparatus to increase common-mode transient immunity in isolation devices is disclosed. An example apparatus includes a current mirror including an input terminal and an output terminal; a transistor including a gate terminal, a first current terminal, and a second current terminal, the gate terminal coupled to a reference voltage terminal, the first current terminal coupled to the input terminal of the current mirror, and the second current terminal coupled to an input node; a buffer including an input terminal and an output terminal, the input terminal of the buffer coupled to the output terminal of the current mirror; and a logic gate including an input terminal and an output terminal, the input terminal of the logic gate coupled to the output terminal of the buffer.

Abstract: Methods, systems, and apparatus to increase common-mode transient immunity in isolation devices is disclosed. An example apparatus includes a current mirror including an input terminal and an output terminal; a transistor including a gate terminal, a first current terminal, and a second current terminal, the gate terminal coupled to a reference voltage terminal, the first current terminal coupled to the input terminal of the current mirror, and the second current terminal coupled to an input node; a buffer including an input terminal and an output terminal, the input terminal of the buffer coupled to the output terminal of the current mirror; and a logic gate including an input terminal and an output terminal, the input terminal of the logic gate coupled to the output terminal of the buffer.

Abstract: Disclosed examples include flyback converters, control circuits and methods to facilitate secondary side regulation of the output voltage. A primary side control circuit operates a primary side switch to independently initiate power transfer cycles to deliver power to a transformer secondary winding in a first mode. A secondary side control circuit operates a synchronous rectifier or secondary side switch to generate a predetermined cycle start request signal via a transformer auxiliary winding to assume secondary side regulation and to cause the primary side controller to initiate new power transfer cycles.

Abstract: Disclosed examples include flyback converters, control circuits and methods to facilitate secondary side regulation of the output voltage. A primary side control circuit operates a primary side switch to independently initiate power transfer cycles to deliver power to a transformer secondary winding in a first mode. A secondary side control circuit operates a synchronous rectifier or secondary side switch to generate a predetermined cycle start request signal via a transformer auxiliary winding to assume secondary side regulation and to cause the primary side controller to initiate new power transfer cycles.

Abstract: Disclosed examples include flyback converters, control circuits and methods to facilitate secondary side regulation of the output voltage. A primary side control circuit operates a primary side switch to independently initiate power transfer cycles to deliver power to a transformer secondary winding in a first mode. A secondary side control circuit operates a synchronous rectifier or secondary side switch to generate a predetermined cycle start request signal via a transformer auxiliary winding to assume secondary side regulation and to cause the primary side controller to initiate new power transfer cycles.