Abstract: A log-structured block system is provided in which writing log-structured data is done. Subsequently, data mirroring is done. In addition, a data storage system for implementing the log-structured block system is provided.

Abstract: Either the disc drive controller or an external software component can divide the storage space on the disc drive into a plurality of different logical components. The disc drive controller also stores parameters that indicate a property data stored in each one of the logical containers. This allows the external software component to access this drive management data, and it allows the block oriented disc drives, themselves, to greatly enhance the efficiency with which data is accessed on the disc drive. The present invention can also be implemented as a method of accessing information on a block oriented disc drive.

Abstract: A log-structured block system is provided in which writing log-structured data is done. Subsequently data mirroring is done. In addition, a data storage system for implementing the log-structured block system is provided.

Abstract: A storage application programming interface (SAPI) engine is included in a hard disk drive (HDD). The SAPI engine operation is based on intelligent recognition of a plurality of different data objects characterized by type and/or size. The SAPI engine assigns a SAPI descriptor to data objects during its analysis recognition process. The SAPI descriptor identifies the type of the data object, and is used by the HDD to map the data object to a unique logical object address (LOA) space of the HDD tailored to characteristics of the particular disk drive. Using the SAPI descriptor assigned by the SAPI engine enables the HDD to more efficiently store data objects being sent by applications on a host computing system to the disk drive. The efficient storage by the HDD provides a system having improved access performance.

Abstract: A parser for reading bits of a packet has a set of logic circuits implemented in a computer chip; a memory interacting with the computer chip, the memory providing first data to the set of logic circuits; means for reading bits from any field of packet into the set of logic circuits, the bits providing second data to the set of logic circuits; means, responsive to the first data and the second data, for the logic circuits to interpret bits of the packet.

Abstract: A multimedia system for delivering multimedia content items to customer premises equipment via a circuit of a communications network includes a plurality of substantially identical nodes connected in a symmetric mesh. Each node includes a switch and a server. The server includes disk storage for the multimedia content, a switch interface for connecting the server to the switch, and a network adapter for connecting the server to the communications network. Source nodes fetch data from disk, routing nodes transport data among nodes, and destination nodes transport the data to the communications network. The switch is a store-and-forward switch including direct memory access engine for pulling data into the switch, and a buffer for storing data to be forwarded to another switch. Portions of each content item are distributed substantially equally over the available storage media to improve load balancing and data redundancy.

Abstract: A network adapter with an interrupt generation circuit to minimize the number of host computer system interrupts needed to notify the host computer system that the network adapter has consumed one or more host memory buffers. The interrupt generation circuit issues an interrupt to the host computer system when the host computer system has entered both a transmit sleep state and a receive sleep state, and the network adapter has consumed a host memory buffer not processed by the host computer system. When the host computer system has no work to do with respect to transmit buffers in the host computer memory, it enters a transmit sleep state and indicates to the network adapter the last transmit buffer it processed. When the host computer system has no work to do with respect to receive buffers in the host computer memory, it enters a receive sleep state and indicates to the network adapter the last receive buffer it processed.

Abstract: In a network adapter for a host computer, the data occupancy level of a buffer memory used to store network packets is monitored, and the occupancy level is reported to the host. The buffer memory is organized as a plurality of fixed-size pages. A memory controller uses an allocation counter to track the number of pages available to store incoming data packets, and the value of the allocation counter is compared with a programmable threshold. A data word accompanies each packet delivered to the host to indicate whether the allocation count exceeds the threshold. When the buffer memory has insufficient free space to store an incoming packet, the packet is discarded. The network adapter keeps a count of the number of discarded packets. An adapter manager microprocessor, which is part of the network adapter, reports the count to the host computer on request. The adapter manager also reports the value of the allocation count and other important network adapter variables to the host computer.

Abstract: An apparatus for memory management in network systems provides added margins of reliability for the receipt of vital maintenance operations protocol (MOP) and station management packets (SMP). In addition, additional overflow allocations of buffers are assigned for receipt of critical system packets which otherwise would typically be discarded in the event of a highly congested system. Thus, if a MOP or a SMP packet is received from the network when the allocated space for storing these types of packets in full, the packets are stored in the overflow allocations, and thus the critical packets are not lost.

Abstract: A monitor for packets on a local area network includes a set of logic circuits implemented in a computer chip, a memory interacting with the computer chip to provide monitoring data to the logic circuits, logic for receiving a packet from the local area network, and a parser to process bits of the packet as they are received, wherein the parser uses the monitoring data in conjunction with the received bits to provide forwarding data which indicates the type of packet received. The monitor uses the forwarding data to determine whether the received packet is stored in memory, discarded, or forwarded to other host computers in the network. The monitor uses type information from the forwarding data to maintain count information of the different types of packets which may be forwarded to a host computer or a remote monitoring device.

Abstract: A method and apparatus for transferring packets of information with different attributes from a device interface to buffers in a host memory dedicated to particular attribute values or ranges of values. The apparatus consists of multiple shared data structures in the form of receive rings, each associated with memory buffers dedicated to a particular range of values for a particular packet attribute. The device interface determines which receive ring is associated with a buffer dedicated to the proper attribute value range by comparing the value of the attribute of the received packet with the values of attributes associated with the buffers of each ring. A sequencing ring is provided to store the order in which each receive ring must be accessed by the host cpu when retrieving packets. This sequencing ring ensures that the host cpu will retrieve the packets in the order in which they were received.

Abstract: A network adapter with high throughput data transfer circuit to optimize network data transfers, with host receive ring resource monitoring and reporting is disclosed. Time critical network data is transferred between the network adapter and the host computer system by means of a high throughput data transfer circuit. The high throughput data transfer circuit is designed to provide throughput equal to the bandwidth of a high speed local area network such as the Fiber Distributed Data Interconnect. The high throughput data transfer circuit will inform the local intelligence of the network adapter if the network adapter has used up all host computer system memory allocated for storing data received from the network. Adapter management data is transferred between the network adapter and the host computer system local area network through a lower throughput data transfer circuit.

Abstract: A circulating shift register memory, particularly adaptable to charge coupled device technology, wherein a plurality of circulating shift registers are arranged to provide a matrix of data bits accessible at a common data front. Address counter circuitry cooperating with the register clocking circuits selects a particular bit location on the data front for each shift of the shift registers. Depending upon a mode signal and beginning address from a host system, the address counter circuitry provides successive accesses in predetermined patterns, for example along a row, column or diagonal of the bit matrix.

Abstract: This disclosure relates to fast access CCD memory organizations with parallel loops or tracks wherein the total number of data bits which can be stored on a single calculator chip is dependent on the overhead circuitry consisting of a number of refresh amplifiers and various switches required to switch the stored data from a storage track to a read/write location and also on the number of refresh amplifiers as well as control circuitry required for distribution of clock pulses to the respective storage tracks. As the number of switches and refresh amplifiers is increased, so is the total area required for storage bits. As the number of clock switches is increased, the power dissipation for the semiconductor chip is decreased. As the number of refresh amplifiers is increased, the access time and total service time is decreased. A number of different optimum memory organizations are disclosed.

Abstract: This disclosure relates to fast access CCD memory organizations with parallel loops or tracks wherein the total number of data bits which can be stored on a single calculator chip is dependent on the overhead circuitry consisting of a number of refresh amplifiers and various switches required to switch the stored data from a storage track to a read/write location and also on the number of refresh amplifiers as well as control circuitry required for distribution of clock pulses to the respective storage tracks. As the number of switches and refresh amplifiers is increased, so is the total area required for storage bits. As the number of clock switches is increased, the power dissipation for the semiconductor chip is decreased. As the number of refresh amplifiers is increased, the access time and total service time is decreased. A number of different optimum memory organizations are disclosed.

Abstract: This disclosure relates to fast access CCD memory organizations with parallel loops or tracks wherein the total number of data bits which can be stored on a single calculator chip is dependent on the overhead circuitry consisting of a number of refresh amplifiers and various switches required to switch the stored data from a storage track to a read/write location and also on the number of refresh amplifiers as well as control circuitry required for distribution of clock pulses to the respective storage tracks. As the number of switches and refresh amplifiers is increased, so is the total area required for storage bits. As the number of clock switches is increased, the power dissipation for the semiconductor chip is decreased. As the number of refresh amplifiers is increased, the access time and total service time is decreased. A number of different optimum memory organizations are disclosed.

Abstract: This disclosure relates to error correcting circuits and methods employed thereby for shift register type memories which are formed of a plurality of loops that may be accessed in parallel. Such circuitry is designed to detect when the output of a given loop or shift register becomes a series of ones or a series of zeros which conditions indicate burst mode error. The data bit corresponding to the loop or shift register producing the error is then corrected by complementation.