Patents by Inventor Satish M. Thatte

Satish M. Thatte has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5437027
    Abstract: A system and method for database management for providing support for long-term storage and retrieval of objects created by application programs written at least in part in object-oriented programming languages consists of a plurality of software modules. These modules provide data definition language translation, object management, object translation, and persistent object storage service. Such system implements an object fault capability to reduce the number of interactions between the application, the database management system, and the database.
    Type: Grant
    Filed: August 20, 1993
    Date of Patent: July 25, 1995
    Assignee: Texas Instruments Incorporated
    Inventors: Thomas J. Bannon, Stephen J. Ford, Vappala J. Joseph, Edward R. Perez, Robert W. Peterson, Diana M. Sparacin, Satish M. Thatte, Carig W. Thompson, Chung C. Wang, David L. Wells
  • Patent number: 5297279
    Abstract: A system and method for database management for providing support for long-term storage and retrieval of objects created by application programs written at least in part in object-oriented programming languages consists of a plurality of software modules. These modules provide data definition language translation, object management, object translation, and persistent object storage service. Such system implements an object fault capability to reduce the number of interactions between the application, the database management system, and the database.
    Type: Grant
    Filed: May 30, 1990
    Date of Patent: March 22, 1994
    Assignee: Texas Instruments Incorporated
    Inventors: Thomas J. Bannon, Stephen J. Ford, Vappala J. Joseph, Edward R. Perez, Robert W. Peterson, Diana M. Sparacin, Satish M. Thatte, Craig W. Thompson, Chung C. Wang, David L. Wells
  • Patent number: 5008786
    Abstract: A recoverable virtual memory for a computer system takes periodic checkpoints which capture the state of the virtual memory. If a system failure occurs, the system can be rolled back to the checkpointed state and restarted. A mechanism for tracking which virtual pages are contained in the checkpointed state discards pages which have been modified since the checkpointed state was saved. Only versions of pages which are saved in the checkpointed state are used in the restore process.
    Type: Grant
    Filed: November 19, 1986
    Date of Patent: April 16, 1991
    Assignee: Texas Instruments Incorporated
    Inventor: Satish M. Thatte
  • Patent number: 4985829
    Abstract: A cache hierarchy to be managed by a memory management unit (MMU) combines the advantages of logical and virtual address caches by providing a cache hierarchy having a logical address cache backed up by a virtual address cache to achieve the performance advantage of a large logical address cache, and the flexibility and efficient use of cache capacity of a large virtual address cache. A physically small logical address cache is combined with a large virtual address cache. The provision of a logical address cache enables reference count management to be done completely by the controller of the virtual address cache and the memory management processor in the MMU. Since the controller of the logical address cache is not involved in the overhead associated with reference counting, higher performance is accomplished as the CPU-MMU interface is released as soon as the access to the logical address cache is completed.
    Type: Grant
    Filed: June 26, 1987
    Date of Patent: January 15, 1991
    Assignee: Texas Instruments Incorporated
    Inventors: Satish M. Thatte, Donald W. Oxley
  • Patent number: 4853842
    Abstract: A uniform memory system for use with symbolic computers has a very large virtual address space. No separate files, not directly addressable in the address space of the virtual memory, exist. A special object, the peristent root, defines memory objects which are relatively permanent, such objects being traceable by pointers from the persistent root. A tombstone mechanism is used to prevent objects from referencing deleted objects.
    Type: Grant
    Filed: February 19, 1988
    Date of Patent: August 1, 1989
    Assignee: Texas Instruments Incorporated
    Inventors: Satish M. Thatte, Donald W. Oxley
  • Patent number: 4814971
    Abstract: Periodic checkpoints are taken of the state of a computer system and its virtual memory. If a system crash occurs, the machine state can be rolled back to the checkpoint state and normal operation restarted. Pages of virtual memory are timestamped to indicate whether they are included in the checkpoint state. Modifications made after the checkpoint time are discarded when the system state is rolled back to the saved checkpoint state. Some recordkeeping is maintained outside of the virtual memory address space in order to assist with the recovery process.
    Type: Grant
    Filed: September 11, 1985
    Date of Patent: March 21, 1989
    Assignee: Texas Instruments Incorporated
    Inventor: Satish M. Thatte
  • Patent number: 4797810
    Abstract: An incremental garbage collector for use in conjunction with a virtual memory, operates on selected generations of an area upon objects which are contained in a semispace, oldspace or newspace, and during the garbage collection process, all accessible objects are copied from the oldspace to the newspace. The garbage collection process occurs in four phases. In the "flip" phase oldspace and newspace of each generation are exchanged. In the "trace" phase, the pointers which are part of a root set of the generation being collected are traced and all oldspace objects referenced by the pointers are copied to newspace, and the pointers in the root set are updated. All copied objects are then "scavenged" to update any pointers in the cells of the copied objects, and to copy to newspace all oldspace objects referenced by those pointers. Finally a "cleaning oldspace" phase is performed as a low-priority background process to purge the entries for the virtual pages on which "obsolete" pointers reside.
    Type: Grant
    Filed: June 26, 1986
    Date of Patent: January 10, 1989
    Assignee: Texas Instruments Incorporated
    Inventors: Timothy J. McEntee, Robert W. Bloemer, Donald W. Oxley, Satish M. Thatte
  • Patent number: 4775932
    Abstract: A memory system for association with a user processor for operation independently from the user processor includes a physical memory and an interface unit for enabling the associated user processor to access the physical memory. The physical memory is represented in a virtual address space which is garbage collected in parallel with the operation of the user processor. The garbage collection process includes reference count deallocation and a garbage collection algorithm for deallocating cyclic structures not deallocated by the reference count process. The reference count process includes providing for a reference count indicating the number of pointer references to a memory block in the virtual address space. When the reference count becomes zero, and no other references to a memory block exist, the block may be freed. In the garbage collection algorithm, the virtual memory space is traced in areas, called OLDSPACE, and compactly copied into a new area, called NEWSPACE.
    Type: Grant
    Filed: July 31, 1984
    Date of Patent: October 4, 1988
    Assignee: Texas Instruments Incorporated
    Inventors: Donald W. Oxley, Timothy J. McEntee, Satish M. Thatte
  • Patent number: 4660130
    Abstract: A method for compacting blocks of memory in a demand paged virtual address space which includes a plurality of virtual address pages includes identifying active and stable blocks to be compacted by defining a pointer to indicate a page of the virtual memory space, and advancing the pointer to continually indicate the page of the beginning of the available virtual memory space. As new blocks are allocated, they are located in the virtual address space beginning at the next available location of the advancing pointer. As blocks are referenced by the user, they are moved to the current location of the advancing pointer, so that, stable blocks may be collected together on stable pages and active blocks are collected together on active pages. A disk memory is provided, and periodically the pages containing collected stable blocks are "paged-out" to it.
    Type: Grant
    Filed: July 24, 1984
    Date of Patent: April 21, 1987
    Assignee: Texas Instruments Incorporated
    Inventors: David H. Bartley, Timothy J. McEntee, Donald W. Oxley, Satish M. Thatte
  • Patent number: 4597080
    Abstract: A method and apparatus for testing VLSI processors using a bit-sliced bus-oriented data path include data and control monitors and BIT for the on-chip memory. The data monitor is used to compress output data produced by the data path. BIT implementation of a functional test coupled with the data monitor are used for an off-line self-test of the data path in field. The control monitor is used to decouple the testing task of the control section from that of the data path.
    Type: Grant
    Filed: November 14, 1983
    Date of Patent: June 24, 1986
    Assignee: Texas Instruments Incorporated
    Inventors: Satish M. Thatte, Thirumalai Sridhar, David S. Ho, Han-Tzong Yuan, Theo J. Powell
  • Patent number: 4594711
    Abstract: A test circuit, called a universal testing block (UTB) for on-chip testing of a VLSI subsystem such as a ROM or an ALU has several modes, including test generator and test evaluator, formed on the VLSI chip. The test generator circuit includes means for applying a predetermined test pattern to an input channel of the subsystem and may be a generator for generating pseudorandom test patterns for application to the subsystem. Alternatively, the test generator may be a counter which can be selectively activated to generate a binary up-count. The UTB also has a shift register mode having a serial input and output to enable serial data to be shifted into and out of the subsystem in parallel fashion. The test evaluator circuit receives output signals from the subsystem, and includes a parallel signature analyzer to generate a signature of the subsystem after the application of the test patterns by the input circuit to indicate whether the subsystem is fault-free.
    Type: Grant
    Filed: November 10, 1983
    Date of Patent: June 10, 1986
    Assignee: Texas Instruments Incorporated
    Inventor: Satish M. Thatte