Patents by Inventor Satish Padmanabhan

Satish Padmanabhan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240135200
    Abstract: One or more structural equations modeling a physical process over time may be sampled using simulated parameter values to generate input data signal values. A noise generator may be applied to the input data signal values to generate noise values. The noise values and the input data signal values may be combined to determined noisy data signal values. These noisy data signal values may in turn be used in combination with one or more states to train a prediction model.
    Type: Application
    Filed: October 18, 2022
    Publication date: April 25, 2024
    Applicant: DIMAAG-AI, Inc.
    Inventors: Rajaram Kudli, Satish Padmanabhan, Fuk Ho Pius Ng, Nagarjun Pogakula Surya Prakash, Ananda Shekappa Sonnada
  • Patent number: 11954929
    Abstract: The failure modes of mechanical components may be determined based on text analysis. For example, a word embedding may be determined based on a plurality of text documents that include a plurality of maintenance records characterizing failure of mechanical components. A vector representation for a particular maintenance record may then be determined based on the word embedding. Based on the vector representation, the particular maintenance record may then be identified as belonging to a particular failure mode out of a set of possible failure modes.
    Type: Grant
    Filed: March 17, 2023
    Date of Patent: April 9, 2024
    Assignee: DIMAAG-AI, Inc.
    Inventors: Rajaram Kudli, Satish Padmanabhan, Fuk Ho Pius Ng
  • Publication number: 20240053739
    Abstract: Remaining useful life may be estimated for a machine component by training a prediction model, even when limited data from actual failures is available. Feature data such as sensor readings associated with a mechanical process may be collected over time. Such readings may be paired with estimates of remaining useful life, for instance as extracted from unstructured text of maintenance records. Such data may be used to train and test the prediction model.
    Type: Application
    Filed: March 17, 2023
    Publication date: February 15, 2024
    Applicant: DIMAAG-AI, Inc.
    Inventors: Rajaram Kudli, Satish Padmanabhan, Fuk Ho Pius Ng
  • Publication number: 20240054800
    Abstract: The failure modes of mechanical components may be determined based on text analysis. For example, a word embedding may be determined based on a plurality of text documents that include a plurality of maintenance records characterizing failure of mechanical components. A vector representation for a particular maintenance record may then be determined based on the word embedding. Based on the vector representation, the particular maintenance record may then be identified as belonging to a particular failure mode out of a set of possible failure modes.
    Type: Application
    Filed: March 17, 2023
    Publication date: February 15, 2024
    Applicant: DIMAAG-AI, Inc.
    Inventors: Rajaram Kudli, Satish Padmanabhan, Fuk Ho Pius Ng
  • Publication number: 20240027974
    Abstract: A first plurality of predictor values occurring during or before a first time interval may be received. An estimated outcome value may be determined for a second time interval by applying a prediction model via a processor to the first plurality of predictor values. A designated outcome value occurring during the second time interval and a second plurality of predictor values occurring during or before the second time interval may be received. An error value may be determined based on the estimated outcome value and the designated outcome value. A drift value for a second time interval may be determined by fitting a function to the second plurality of predictor values. The prediction model may be updated when it is determined that the drift value exceeds a designated drift threshold or that the error value exceeds a designated error threshold.
    Type: Application
    Filed: June 30, 2023
    Publication date: January 25, 2024
    Applicant: DIMAAG-AI, Inc.
    Inventors: Rajaram Kudli, Satish Padmanabhan, Fuk Ho Pius Ng, Dushyanth Gokhale
  • Patent number: 11783233
    Abstract: A feature data segment may be determined by applying a feature segmentation model to a test data observation. The feature segmentation model may be pre-trained via a plurality of training data observations and may divide the plurality of training data observations into a plurality of feature data segments. A predicted target value may be determined by applying to a test data observation a prediction model pre-trained via a plurality of training data observations. One or more distance metrics representing a respective distance between the test data observation and the feature data segment along one or more dimensions may be determined. The one or more distance metrics may be represented in a user interface. An updated prediction model and an updated feature segmentation model that both incorporate the test data observation and the training data observations may be determined based on user input.
    Type: Grant
    Filed: January 11, 2023
    Date of Patent: October 10, 2023
    Assignee: DIMAAG-AI, Inc.
    Inventors: Rajaram Kudli, Satish Padmanabhan, Fuk Ho Pius Ng, Nagarjun Pogakula Surya Prakash, Ananda Shekappa Sonnada
  • Patent number: 11740905
    Abstract: In many industrial settings, a process is repeated many times, for instance to transform physical inputs into physical outputs. To detect a situation involving such a process in which errors are likely to occur, information about the process may be collected to determine time-varying feature vectors. Then, a drift value may be determined by comparing feature vectors corresponding with different time periods. When the drift value crosses a designated drift threshold, a predicted outcome value may be determined by applying a prediction model. Sensitivity values may be determined for different features, and elements of the process may then be updated based at least in part on the sensitivity values.
    Type: Grant
    Filed: July 25, 2022
    Date of Patent: August 29, 2023
    Assignee: DIMAAG-AI, Inc.
    Inventors: Rajaram Kudli, Satish Padmanabhan, Fuk Ho Pius Ng, Dushyanth Gokhale
  • Publication number: 20230195933
    Abstract: In some examples, machine learning and rule-based identification, anonymization, and de-anonymization of sensitive structured and unstructured data may include receiving input data that is to be masked, and determining, for the input data, at least one type 1 of entity extraction from a plurality of types of entity extractions to be performed on the input data. The at least one determined type of entity extraction may be performed on the input data, and at least one entity may be extracted from the input data. At least one replacement strategy may be determined from a plurality of replacement strategies for the at least one extracted entity. Further, the at least one determined replacement strategy may be applied to the at least one extracted entity to generate masked data.
    Type: Application
    Filed: December 17, 2021
    Publication date: June 22, 2023
    Applicant: ACCENTURE GLOBAL SOLUTIONS LIMITED
    Inventors: Aishwarya SATISH PADMANABHAN, Anshuma CHANDAK, Emmanuel MUNGUIA TAPIA
  • Patent number: 11676036
    Abstract: Systems and methods are disclosed for training a previously trained neural network with incremental dataset. Original train data is provided to a neural network and the neural network is trained based on the plurality of classes in the sets of training data and/or testing data. The connected representation and the weights of the neural network is the model of the neural network. The trained model is to be updated for an incremental train data. The embodiments provide a process by which the trained model is updated for the incremental train data. This process creates a ground truth for the original training data and trains on the combined set of original train data and the incremental train data. The incremental training is tested on a test data to conclude the training and to generate the incremental trained model, minimizing the knowledge learned with the original data. Thus, the results remain consistent with the original model trained by the original dataset except the incremental train data.
    Type: Grant
    Filed: May 21, 2020
    Date of Patent: June 13, 2023
    Assignee: DIMAAG-AI, Inc.
    Inventors: Nagarjun Pogakula Surya, Gomathi Sankar, Fuk Ho Pius Ng, Satish Padmanabhan
  • Patent number: 11636697
    Abstract: The failure modes of mechanical components may be determined based on text analysis. For example, a word embedding may be determined based on a plurality of text documents that include a plurality of maintenance records characterizing failure of mechanical components. A vector representation for a particular maintenance record may then be determined based on the word embedding. Based on the vector representation, the particular maintenance record may then be identified as belonging to a particular failure mode out of a set of possible failure modes.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: April 25, 2023
    Assignee: DIMAAG-AI, Inc.
    Inventors: Rajaram Kudli, Satish Padmanabhan, Fuk Ho Pius Ng
  • Patent number: 11635753
    Abstract: Remaining useful life may be estimated for a machine component by training a prediction model, even when limited data from actual failures is available. Feature data such as sensor readings associated with a mechanical process may be collected over time. Such readings may be paired with estimates of remaining useful life, for instance as extracted from unstructured text of maintenance records. Such data may be used to train and test the prediction model.
    Type: Grant
    Filed: August 15, 2022
    Date of Patent: April 25, 2023
    Assignee: DIMAAG-AI, Inc.
    Inventors: Rajaram Kudli, Satish Padmanabhan, Fuk Ho Pius Ng
  • Publication number: 20220261628
    Abstract: A method of processing data for an artificial intelligence (AI) system includes extracting features of the data to produce a lower dimensional representation of the data points; grouping the lower dimensional representation into clusters using a clustering algorithm; comparing the classes of data points within the clusters; and identifying unrepresented, under-represented, or misrepresented data.
    Type: Application
    Filed: February 15, 2021
    Publication date: August 18, 2022
    Inventors: Nagarjun Pogakula Surya, Gomathi Sankar, Fuk Ho Pius Ng, Satish Padmanabhan, Manikandan Manikam
  • Publication number: 20210365793
    Abstract: Systems and methods are disclosed for training a previously trained neural network with incremental dataset. Original train data is provided to a neural network and the neural network is trained based on the plurality of classes in the sets of training data and/or testing data. The connected representation and the weights of the neural network is the model of the neural network. The trained model is to be updated for an incremental train data. The embodiments provide a process by which the trained model is updated for the incremental train data. This process creates a ground truth for the original training data and trains on the combined set of original train data and the incremental train data. The incremental training is tested on a test data to conclude the training and to generate the incremental trained model, minimizing the knowledge learned with the original data. Thus, the results remain consistent with the original model trained by the original dataset except the incremental train data.
    Type: Application
    Filed: May 21, 2020
    Publication date: November 25, 2021
    Inventors: Nagarjun Pogakula Surya, Gomathi Sankar, Fuk Ho Pius Ng, Satish Padmanabhan
  • Publication number: 20180174251
    Abstract: One variation of a method for automating negotiation of goods includes: initiating a transaction negotiation package specifying a restaurant, a reservation date and time, a selection of items, and an initial monetary offer for the set of items selected by a user; retrieving a target discount rate associated with the restaurant and an aggregate discount rate negotiated across transactions previously completed with the restaurant; selecting a maximum discount rate for the transaction negotiation package based on a difference between the preset target discount rate and the aggregate discount rate; if the initial monetary offer represents an initial discount rate greater than the maximum discount rate, serving a first monetary counter offer—representing a first counter discount rate less than the maximum discount rate—to the user; and processing payment for the selection of items according to the first monetary counter offer if the first monetary counter offer is accepted.
    Type: Application
    Filed: December 16, 2016
    Publication date: June 21, 2018
    Inventors: Satish Padmanabhan, Fuk Ho Pius Ng, Lisa Higa, Christine Renschler, Yashwant Sakarchand Kothari, Abinaya Senthil, Shalini Satish
  • Publication number: 20140082325
    Abstract: Systems and methods are disclosed to automatically generate a processor architecture for a custom integrated circuit (IC) described by a computer readable code. The IC has one or more timing and hardware constraints. The system extracts parameters defining the processor architecture from a static profile and a dynamic profile of the computer readable code; iteratively optimizes the processor architecture by changing one or more parameters until all timing and hardware constraints expressed as a cost function are met; and synthesizes the generated processor architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication.
    Type: Application
    Filed: March 1, 2013
    Publication date: March 20, 2014
    Inventors: Anand Pandurangan, Satish Padmanabhan, Siva Selvaraj, Ananth Durbha, Suresh Kadiyala, Pius Ng, Sanjay Banerjee
  • Publication number: 20130346926
    Abstract: Systems and methods are disclosed to automatically design a custom integrated circuit based on algorithmic process or code as input and using highly automated tools that requires virtually no human involvement is disclosed.
    Type: Application
    Filed: November 9, 2012
    Publication date: December 26, 2013
    Applicant: ALGOTOCHIP CORPORATION
    Inventors: Anand Pandurangan, Satish Padmanabhan, Siva Selvaraj, Shailesh I. Shah, Krishna Kumar Gadiyaram, Gagan Bihari Rath, Fuk Ho Pius Ng, Ananth Durbha, Suresh Kadiyala
  • Patent number: 8589854
    Abstract: Systems and methods are disclosed to manage power in a custom integrated circuit (IC) design by receiving a specification of the custom integrated circuit including computer readable code and generating a profile of the computer readable code to determine instruction usage; automatically generating a processor architecture uniquely customized to the computer readable code, the processor architecture having one or more processing blocks and one or more power domains; determining when each processing block is needed based on the code profile and assigning each block to one of the power domains; and gating the power domains with power based on the code profile; and synthesizing the generated architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication.
    Type: Grant
    Filed: July 13, 2010
    Date of Patent: November 19, 2013
    Assignee: Algotochip Corp.
    Inventors: Pius Ng, Satish Padmanabhan, Anand Pandurangan, Ananth Durbha, Suresh Kadiyala, Gary Oblock
  • Patent number: 8572544
    Abstract: Systems and methods are disclosed to automatically method to manage power in a custom integrated circuit (IC) design with a code profile by receiving an instruction execution sequence based on the code profile and reassigning or delaying the instruction sequence to spread operations or activities over a plurality of processing blocks to reduce hot spots; applying sub-region weight distributions to estimate power hot-spot locations; and synthesizing the generated architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication.
    Type: Grant
    Filed: April 22, 2012
    Date of Patent: October 29, 2013
    Assignee: Algotochip Corp.
    Inventors: Ananth Durbha, Pius Ng, Gary Oblock, Suresh Kadiyala, Satish Padmanabhan
  • Patent number: 8561005
    Abstract: Systems and methods are disclosed to automatically synthesize a custom integrated circuit by automatically generating an application specific instruction set processor architecture uniquely customized to the computer readable code with a compiler-in-the-loop to compile, assemble and link code for each processor architecture iteration, the processor architecture having one or more processing blocks on the IC executing one or more instructions; and synthesizing the generated architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication.
    Type: Grant
    Filed: April 22, 2012
    Date of Patent: October 15, 2013
    Assignee: Algotochip Corp.
    Inventors: Ananth Durbha, Pius Ng, Gary Oblock, Suresh Kadiyala, Satish Padmanabhan
  • Publication number: 20130263067
    Abstract: Systems and methods are disclosed to automatically design a custom integrated circuit by receiving a specification of the custom integrated circuit including computer readable code and one or more constraints on the custom integrated circuit; automatically generating a computer architecture with programmable processor and one or more co-processors for the computer readable code that best fits the constraints; automatically determining an instruction execution sequence based on the code profile and reassigning or delaying the instruction sequence to spread operation over one or more processing blocks to reduce hot spots; automatically generating associated test suites and vectors for the computer readable code on the custom integrated circuit; and automatically synthesizing the designed architecture and generating a computer readable description of the custom integrated circuit for semiconductor fabrication.
    Type: Application
    Filed: September 25, 2012
    Publication date: October 3, 2013
    Applicant: ALGOTOCHIP CORPORATION
    Inventors: Satish Padmanabhan, Pius Ng, Anand Pandurangan, Suresh Kadiyala, Ananth Durbha, Tak Shigihara