Abstract: Various systems and methods for content adaptation based on seat position or occupant position in a vehicle are described herein. An example implementation for content adaptation based on seat position in a vehicle includes: obtaining sensor data, the sensor data including a seat position of a seat in the vehicle; identifying audiovisual content for output to a human occupant in the vehicle; identifying an occupant position of the human occupant, based on the seat position, for a user experience of the output of the audiovisual content; and cause one or more adjustments to the output of the audiovisual content in the vehicle, via an output device, based on the identified position of the human occupant.

Abstract: A DTaaS architecture is described to support communication-side optimization and to reduce communication overhead while meeting necessary reliability and latency requirements. The disclosure describe techniques for utilizing DT resources for V2X environments using both virtual and physical “twin” resources to achieve improved resiliency. Moreover, to optimize redundancy costs, the ratio of virtual DT nodes to physical DT nodes may be asymmetrical. An asymmetric approach to DT redundancies involving both virtual and physical resources enables greater flexibility in managing deployment costs.

Abstract: Systems, apparatus, articles of manufacture, and methods are disclosed for in-network computation and control of network congestion based on in-network computation delays. An example device includes interface circuitry to access a packet including a header having (1) a destination address field to identify a first network address of a destination device capable of performing an action and (2) a workload class field to identify a workload class associated with the action. The example device also includes programmable circuitry to utilize machine-readable instructions to perform the action at the device based on the workload class field, the device having a second network address that is different than the first network address. Additionally, the example programmable circuitry is to modify an indicator field of the packet to indicate that the action has been performed and cause the interface circuitry to forward the packet with the modified indicator field toward the destination device.

Abstract: The invention relates to a system that implements application lineage metadata and registration. An embodiment of the present invention is directed to auto-generating Application Lineage data. This may be accomplished by implementing code markers, such as @Annotations, within the code. An embodiment of the present invention may scan the code each time a build is kicked off by a continuous integration and continuous delivery (CI/CD) pipeline. At the end of the build, the documentation may be automatically generated with application lineage information.

Abstract: The invention relates to a system that implements application lineage metadata and registration. An embodiment of the present invention is directed to auto-generating Application Lineage data. This may be accomplished by implementing code markers, such as @Annotations, within the code. An embodiment of the present invention may scan the code each time a build is kicked off by a continuous integration and continuous delivery (CI/CD) pipeline. At the end of the build, the documentation may be automatically generated with application lineage information.

Abstract: The invention relates to a system that implements application lineage metadata and registration. An embodiment of the present invention is directed to auto generating Application Lineage data. This may be accomplished by implementing code markers, such as @Annotations, within the code. An embodiment of the present invention may scan the code each time a build is kicked off by a continuous integration and continuous delivery (CI/CD) pipeline. At the end of the build, the documentation may be automatically generated with application lineage information.

Abstract: The invention relates to a system that implements application lineage metadata and registration. An embodiment of the present invention is directed to auto generating Application Lineage data. This may be accomplished by implementing code markers, such as @Annotations, within the code. An embodiment of the present invention may scan the code each time a build is kicked off by a continuous integration and continuous delivery (CI/CD) pipeline. At the end of the build, the documentation may be automatically generated with application lineage information.

Abstract: A system includes a processing core built on a semiconductor substrate, the processing core having a first sub core and a second sub core, each of the first and second sub cores configured to perform a processing function, and a plurality of power rails traversing a dimension of the processing core and spanning from the first sub core to the second sub core, each of the power rails being configured to provide an operating voltage to the first and second sub cores, and wherein a boundary between the first sub core and the second sub core is irregularly shaped, and wherein each of the first and second sub cores corresponds to a respective power domain.

Abstract: Embodiments relate to physically implementing an integrated circuit design while conforming to complex design rule constraints. According to some aspects, embodiments relate to an automated method for generating shapes for correcting design rule errors such as line end-to-end spacing violations. In these and other embodiments, the automated method determines the errors post-placement and automatically generates the required shapes, taking into account additional process design rules and neighboring shapes. Some embodiments consider clusters of objects, potential legal areas between line-ends, merging of potential legal areas and generation of various shapes to produce a design rule correct layout.

Abstract: A semiconductor device includes: a processing core having a plurality of sub cores, a plurality of power rails spanning from a first sub core to a second sub core of the plurality of sub cores, the plurality of power rails configured to provide an operating voltage to each of the first sub core and the second sub core, and a plurality of cells defining a boundary between the first sub core and the second sub core, each of the cells providing a discontinuity in a respective power rail, wherein the discontinuity includes a break in the respective power rail in more than one layer of the semiconductor device.

Abstract: A system includes a processing core built on a semiconductor substrate, the processing core having a first sub core and a second sub core, each of the first and second sub cores configured to perform a processing function, and a plurality of power rails traversing a dimension of the processing core and spanning from the first sub core to the second sub core, each of the power rails being configured to provide an operating voltage to the first and second sub cores, and wherein a boundary between the first sub core and the second sub core is irregularly shaped, and wherein each of the first and second sub cores corresponds to a respective power domain.

Abstract: A semiconductor device includes: a processing core having a plurality of sub cores, a plurality of power rails spanning from a first sub core to a second sub core of the plurality of sub cores, the plurality of power rails configured to provide an operating voltage to each of the first sub core and the second sub core, and a plurality of cells defining a boundary between the first sub core and the second sub core, each of the cells providing a discontinuity in a respective power rail, wherein the discontinuity includes a break in the respective power rail in more than one layer of the semiconductor device.

Abstract: Various embodiments implement additional connectivity for electronic designs by identifying one or more regions for a route in normal connectivity of an electronic design, identifying a plurality of seeding segments from the route based at least in part upon the one or more regions, identifying a plurality of additional nodes in the plurality of seeding segments, and generating one or more additional routes connecting the plurality of additional nodes in the plurality of seeding segments. The one or more additional routes are generated without disturbing the normal connectivity including a plurality of Steiner points and the route. Additional nodes differ from Steiner points and are used to implement additional routes that belong to a different route type.

Abstract: One aspect checks and prepares design data (202) based on design rule(s) to identify tracks for physical implementation of an electronic design. Structured physical implementation (204) is performed to implement at least a part of the electronic design by using the tracks under separate design rule(s). Structured physical implementation using the tracks under separate design rules result in correct-by-construction implementation results automatically satisfying the design rule(s), without performing additional design rule checking on the design rule(s). Additional physical implementation (206) may be optionally performed for portion(s) of the electronic design not implemented with the structured physical implementation. Layout fixing or optimization may be optionally performed to fix design rule violations in the additional physical implementation results, if any, or to optimize the additional physical implementation results.

Abstract: One aspect checks and prepares design data (202) based on design rule(s) to identify tracks for physical implementation of an electronic design. Structured physical implementation (204) is performed to implement at least a part of the electronic design by using the tracks under separate design rule(s). Structured physical implementation using the tracks under separate design rules result in correct-by-construction implementation results automatically satisfying the design rule(s), without performing additional design rule checking on the design rule(s). Additional physical implementation (206) may be optionally performed for portion(s) of the electronic design not implemented with the structured physical implementation. Layout fixing or optimization may be optionally performed to fix design rule violations in the additional physical implementation results, if any, or to optimize the additional physical implementation results.

Abstract: Various embodiments implement additional connectivity for electronic designs by identifying one or more regions for a route in normal connectivity of an electronic design, identifying a plurality of seeding segments from the route based at least in part upon the one or more regions, identifying a plurality of additional nodes in the plurality of seeding segments, and generating one or more additional routes connecting the plurality of additional nodes in the plurality of seeding segments. The one or more additional routes are generated without disturbing the normal connectivity including a plurality of Steiner points and the route. Additional nodes differ from Steiner points and are used to implement additional routes that belong to a different route type.

Abstract: Disclosed are methods, systems, and articles of manufacture for assigning track patterns to regions of an electronic design in one or more embodiments. One aspect tessellates an area on a layer of an electronic design that is subject to one or more track pattern requirements and dynamically maintains the tessellation structure from the tessellation process for early stages of the design process such as floorplanning, placement, or routing. Another aspect identifies or creates multiple strips or multiple regions for an area on a layer of an electronic design and assigns or associates a track pattern or a track pattern group to each of the multiple strips or multiple regions. In this latter aspect, a track pattern or a track pattern group is no longer required to apply to the entire layer.

Abstract: Provided are systems and methods for reducing power consumption in the interface and routing circuitry associated with various core modules of an integrated circuit or system. One system includes core modules, glue logic domains adapted to interface the plurality of core modules, and a power controller electrically coupled to the glue logic domains. Each glue logic domain includes a glue logic module implemented as a soft macro with metal traces extending beyond an extent of the glue logic module. The power controller decouples power from selected glue logic domains based on control signals and/or detected power down states of core modules and/or other glue logic domains. The power controller facilitates the power transitions using logic state retention, logic state clamping, ordered or scheduled transitioning, and/or other power transition systems and methods.

Abstract: Various embodiments identify a design including circuit features and identify an operation that produces an aggressor for victim(s). The operation on the aggressor and the set of victims are implemented using local maximally spanning spacetile(s) while satisfying some design requirements. Where the set of victims includes interconnects, the design may allow no bend in some interconnects. One or more spacetiles are used to perform the operation on the aggressor and implement the interconnects while introducing no bends in the interconnects by using local maximally spanning spacetile(s). Some implementation may perform block modeling for the aggressor to perform the operation on the aggressor and implement a set of victims while preserving the relative order of the interconnects by using the block modeling for the aggressor.

Abstract: Various embodiments identify a design including circuit features and identify an operation that produces an aggressor for victim(s). The operation on the aggressor and the set of victims are implemented using local maximally spanning spacetile(s) while satisfying some design requirements. Where the set of victims includes interconnects, the design may allow no bend in some interconnects. One or more spacetiles are used to perform the operation on the aggressor and implement the interconnects while introducing no bends in the interconnects by using local maximally spanning spacetile(s). Some implementation may perform block modeling for the aggressor to perform the operation on the aggressor and implement a set of victims while preserving the relative order of the interconnects by using the block modeling for the aggressor.