Abstract: Cameras are located within the display area of a display. In-display cameras allow for thinner display bezels. In-display cameras allow for the creation of ultra-high resolution images. The ability to capture an object from multiple perspectives allows for holographic image recording and playback. Multiple views of an image can be captured with varying depths of focus, allowing an image's depth of field to be adjusted during post processing. In-display cameras can also be used for user authentication, touch detection and three-dimensional gesture recognition. Thermal sensors located within the display area allow for control of the display temperature, improved control over system performance, and compensation for micro-LED degradation that can occur due to aging or increased temperature. Microlens assemblies located above pixels can adjust the viewing cone angle of the display or a portion of the display and microassemblies located under individual pixels or pixel arrays can adjust a viewing angle.

Abstract: A communication apparatus including a digital processing circuit coupled to a radio frequency (RF) circuit and to a serial communications device. The serial communications device may be configured to buffer data communicated between the digital processing circuit and an external device. A portion of the serial communications device may be disabled during an active mode of operation of the RF circuit. The serial communications device may include a flow control logic circuit configured to control a data stream between the digital processing circuit and the external device while a portion of the serial communications device is disabled. In some embodiments, a portion of the digital processing circuit may be disabled during an active mode of operation of the RF circuit.

Abstract: A communication apparatus including a radio frequency (RF) circuit coupled to a digital processing circuit and an interface circuit coupled to an authentication device. The RF circuit may be configured to operate on a radio frequency signal. A portion of the digital processing circuit may be disabled during an active mode of operation of the RF circuit. The interface circuit may be configured to buffer data communicated between the digital processing circuit and an authentication device during the active mode of operation of the RF circuit. In one embodiment, the interface circuit includes a memory and memory control logic to buffer data available for transmission to and/or received from the authentication device. In some embodiments, the digital processing circuit includes a processing unit configured to process authentication data received from the authentication device. In these and other embodiments, the authentication device may be a subscriber identity module (SIM).

Abstract: A timing and carrier error detector module (127) of a communication receiver (111). The timing and carrier error detector module uses phase information of a correlated signal (e.g. a Barker de-spread signal) to generate a timing signal and carrier error signal. In one example, the phase information includes a phase error signal of the correlated signal. In one example, the timing and carrier error detector module calculates an indication of the variance of the phase error signal for a plurality of sample positions over a plurality of Barker symbol intervals. The timing signal is based upon the sample position having a minimum indication of a variance.

Abstract: Systems and methods are described for providing a reconfigurable circuit having multiple distinct circuit configurations with respective distinct operating modes The circuit may be controllably configures to perform a fast Fourier transform function, a multiplier function, and a divider function. In one exemplary practical application of the invention, the fast Fourier transform function, multiplier function, and divider function may be used for signal demodulation, channel equalization and channel estimation for a WLAN IEEE 802.11 system.

Abstract: Systems and methods are described for providing a reconfigurable circuit having multiple distinct circuit configurations with respective distinct operating modes The circuit may be controllably configures to perform a fast Fourier transform function, a multiplier function, and a divider function. In one exemplary practical application of the invention, the fast Fourier transform function, multiplier function, and divider function may be used for signal demodulation, channel equalization and channel estimation for a WLAN IEEE 802.11 system.