Abstract: A voltage regulator includes a static regulator that provides a static regulated supply output as a reference input to a dynamic regulator to provide a regulated supply voltage. In one embodiment, multiple dynamic regulators are connected to the static regulated supply output of the static regulator. The one or more dynamic regulators dynamically detect when the regulated supply voltage is loaded below a predetermined reference level, and provide extra current in response to prevent the regulated supply voltage from drooping. Since the static regulator is capable of handling large average currents, the dynamic regulator circuit can be smaller than a typical dynamic regulator for an equivalent load. Furthermore, since the dynamic regulator provides transient current requirements, the size of the static regulator may be likewise smaller in size than a typical static regulator for an equivalent load.

Abstract: A reference voltage generator may include an input for receiving a first voltage for input to a sense amp. The reference voltage generator may also include an output for outputting a second voltage for input to the sense amp. The second voltage is influenced by the first voltage. Alternatively, a reference voltage generator may include a first input for receiving a first voltage on a first bitline. The reference voltage generator may also include a first output for outputting a second voltage on a second bitline. The second voltage is influenced by the first voltage. Alternatively, a reference voltage generator may include a first input for receiving a first voltage on a first transmission busline. The voltage generator may also include a first output for outputting a second voltage on a second transmission busline. The second voltage is influenced by the first voltage.

Abstract: A memory device includes a random access memory (RAM) cell accessible through a RAM wordline and coupled between first and second bitlines; a read only memory (ROM) cell accessible through a ROM wordline and having an output coupled to the first bitline and an input configured to receive a first voltage signal; and a reference voltage generator having a first input coupled to the first bitline, a second input configured to receive the first voltage signal, and an output coupled to the second bitline. The memory device may further include a bitline load having an output coupled to the first bitline. A virtual ground driver configured to produce the first voltage signal may be coupled to the input of the read only memory cell. Further, column select pass gates configured to be under the control of a logic signal and having a first input coupled to the first bitline, a second input coupled to the second bitline, a first output and a second output may be provided.