Abstract: Methods and circuits for synthesizing two or more signals phase-locked to a common reference frequency signal are disclosed. In one embodiment, a method comprises generating first and second output signals phase-locked to a reference clock signal, using first and second phase-locked loop circuits. In response to a detected frequency error in the first output signal, the first output signal is corrected by adjusting a frequency-division ratio in the first phase-locked loop circuit. The second output signal is corrected, separately from the correction to the first output signal, by adjusting a frequency-division ratio in the second phase-locked loop circuit, using an adjustment parameter calculated from the detected frequency error. In another exemplary method, first and second output signals are generated as described above, using first and second phase-locked loop circuits.

Abstract: Methods and circuits for synthesizing two or more signals phase-locked to a common reference frequency signal are disclosed. In one embodiment, a method comprises generating first and second output signals phase-locked to a reference clock signal, using first and second phase-locked loop circuits. In response to a detected frequency error in the first output signal, the first output signal is corrected by adjusting a frequency-division ratio in the first phase-locked loop circuit. The second output signal is corrected, separately from the correction to the first output signal, by adjusting a frequency-division ratio in the second phase-locked loop circuit, using an adjustment parameter calculated from the detected frequency error. In another exemplary method, first and second output signals are generated as described above, using first and second phase-locked loop circuits.

Abstract: The wireless device described herein uses a single crystal oscillator to generate the high and low frequency clock signals required by the wireless device during both active and inactive radio communications. An exemplary multi-mode clock unit comprises a single crystal oscillator operable in a normal power mode and a reduced power mode, and a control unit that selectively switches the crystal oscillator between the first and second power modes based on a current clock signal quality requirement. The control unit may selectively switch between the first and second power modes by selectively varying a capacitive load of the crystal oscillator and/or by varying a drive signal of the crystal oscillator. For example, the control unit may select the normal power mode when a cellular transceiver is active, and a reduced power mode when the cellular transceiver is inactive to reduce power consumption during the inactive state.