Patents by Inventor Satish Yeldandi

Satish Yeldandi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190006459
    Abstract: A semiconductor structure includes a III-V semiconductor structure; a first electrode; a first barrier layer disposed over the first electrode; a first adhesion layer disposed over the first electrode; a first passivation layer disposed over the first adhesion layer; a dielectric layer disposed over the first passivation layer; a second passivation layer disposed over the dielectric layer; a second adhesion layer disposed over the second passivation layer; a second barrier layer disposed over the second adhesion layer; and a second electrode disposed over the second barrier layer.
    Type: Application
    Filed: June 28, 2017
    Publication date: January 3, 2019
    Inventors: Satish Yeldandi, Phil Nikkel, Thomas Dungan, Jonathan Abrokwah
  • Patent number: 9966347
    Abstract: The present technology is directed to manufacturing semiconductor dies with under-bump metal (UBM) structures for die-to-die and/or package-to-package interconnects or other types of interconnects. In one embodiment, a method for forming under-bump metal (UBM) structures on a semiconductor die comprises constructing a UBM pillar by plating a first material onto first areas of a seed structure and depositing a second material over the first material. The first material has first electrical potential and the second material has a second electrical potential greater than the first electrical potential. The method further comprises reducing the difference in the electrical potential between the first material and the second material, and then removing second areas of the seed structure between the UBM pillars thereby forming UBM structures on the semiconductor die.
    Type: Grant
    Filed: June 15, 2017
    Date of Patent: May 8, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Brandon P. Wirz, Jaspreet S. Gandhi, Christopher J. Gambee, Satish Yeldandi
  • Publication number: 20170287857
    Abstract: The present technology is directed to manufacturing semiconductor dies with under-bump metal (UBM) structures for die-to-die and/or package-to-package interconnects or other types of interconnects. In one embodiment, a method for forming under-bump metal (UBM) structures on a semiconductor die comprises constructing a UBM pillar by plating a first material onto first areas of a seed structure and depositing a second material over the first material. The first material has first electrical potential and the second material has a second electrical potential greater than the first electrical potential. The method further comprises reducing the difference in the electrical potential between the first material and the second material, and then removing second areas of the seed structure between the UBM pillars thereby forming UBM structures on the semiconductor die.
    Type: Application
    Filed: June 15, 2017
    Publication date: October 5, 2017
    Inventors: Brandon P. Wirz, Jaspreet S. Gandhi, Christopher J. Gambee, Satish Yeldandi
  • Patent number: 9704781
    Abstract: The present technology is directed to manufacturing semiconductor dies with under-bump metal (UBM) structures for die-to-die and/or package-to-package interconnects or other types of interconnects. In one embodiment, a method for forming under-bump metal (UBM) structures on a semiconductor die comprises constructing a UBM pillar by plating a first material onto first areas of a seed structure and depositing a second material over the first material. The first material has first electrical potential and the second material has a second electrical potential greater than the first electrical potential. The method further comprises reducing the difference in the electrical potential between the first material and the second material, and then removing second areas of the seed structure between the UBM pillars thereby forming UBM structures on the semiconductor die.
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: July 11, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Brandon P. Wirz, Jaspreet S. Gandhi, Christopher J. Gambee, Satish Yeldandi
  • Publication number: 20150137353
    Abstract: The present technology is directed to manufacturing semiconductor dies with under-bump metal (UBM) structures for die-to-die and/or package-to-package interconnects or other types of interconnects. In one embodiment, a method for forming under-bump metal (UBM) structures on a semiconductor die comprises constructing a UBM pillar by plating a first material onto first areas of a seed structure and depositing a second material over the first material. The first material has first electrical potential and the second material has a second electrical potential greater than the first electrical potential. The method further comprises reducing the difference in the electrical potential between the first material and the second material, and then removing second areas of the seed structure between the UBM pillars thereby forming UBM structures on the semiconductor die.
    Type: Application
    Filed: November 19, 2013
    Publication date: May 21, 2015
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Brandon P. Wirz, Jaspreet S. Gandhi, Christopher J. Gambee, Satish Yeldandi