Patents by Inventor Satisha Nanjunde Gowda

Satisha Nanjunde Gowda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Memory device having memory cells with enhanced low voltage write capability
    Patent number: 8441842
    Abstract: A memory device includes a memory array comprising a plurality of memory cells. At least a given one of the memory cells comprises a pair of cross-coupled inverters and associated write assist circuitry. The write assist circuitry comprises first switching circuitry coupled between a supply node of a device of the first inverter and a supply node of the memory cell, and second switching circuitry coupled between a supply node of a device of the second inverter and the supply node of the memory cell. The first and second switching circuitry are separately controlled such that during a write operation of the memory cell the supply node of one of the devices is connected to the supply node of the memory cell while the supply node of the other device is not connected to the supply node of the memory cell but is instead permitted to float.
    Type: Grant
    Filed: December 21, 2010
    Date of Patent: May 14, 2013
    Assignee: LSI Corporation
    Inventors: Vinod Rachamadugu, Setti Shanmukheswara Rao, Satisha Nanjunde Gowda
  • Memory Device Having Memory Cells with Enhanced Low Voltage Write Capability
    Publication number: 20120155151
    Abstract: A memory device includes a memory array comprising a plurality of memory cells. At least a given one of the memory cells comprises a pair of cross-coupled inverters and associated write assist circuitry. The write assist circuitry comprises first switching circuitry coupled between a supply node of a device of the first inverter and a supply node of the memory cell, and second switching circuitry coupled between a supply node of a device of the second inverter and the supply node of the memory cell. The first and second switching circuitry are separately controlled such that during a write operation of the memory cell the supply node of one of the devices is connected to the supply node of the memory cell while the supply node of the other device is not connected to the supply node of the memory cell but is instead permitted to float.
    Type: Application
    Filed: December 21, 2010
    Publication date: June 21, 2012
    Inventors: Vinod Rachamadugu, Setti Shanmukheswara Rao, Satisha Nanjunde Gowda