Abstract: Delay calibration for digital signal chains of SFCW systems is disclosed. An example calibration method includes receiving a burst with a test pulse, the burst having a duration of L clock cycles; receiving a trigger indicative of a time when the burst was transmitted; generating a digital signal indicative of the received burst; for each of L clock cycles, computing a moving average of a subset of digital samples and an amplitude for each average; identifying one moving average for which the computed amplitude is closest to an expected amplitude; identifying the clock cycle of the identified moving average; and updating at least one delay to be applied in digital signal processing of received bursts based on a difference between the trigger and the identified clock cycle. The delay may be used for selecting digital samples of the received signal that contain valid data for performing further data processing.

Abstract: A radio timing controller equipped with one or more sequence controllers is disclosed. Sequence controllers enable high degree of programmability of the radio timing controller, e.g., in terms of the number of general purpose input/outputs (GPIOs), mapping of GPIOs to specific radio controls, setting of the radio control output states, timing to sequence events at radio symbol boundaries, etc.

Abstract: Delay calibration for digital signal chains of SFCW systems is disclosed. An example calibration method includes receiving a burst with a test pulse, the burst having a duration of L clock cycles; receiving a trigger indicative of a time when the burst was transmitted; generating a digital signal indicative of the received burst; for each of L clock cycles, computing a moving average of a subset of digital samples and an amplitude for each average; identifying one moving average for which the computed amplitude is closest to an expected amplitude; identifying the clock cycle of the identified moving average; and updating at least one delay to be applied in digital signal processing of received bursts based on a difference between the trigger and the identified clock cycle. The delay may be used for selecting digital samples of the received signal that contain valid data for performing further data processing.

Abstract: A sample rate converter (“SRC”) for implementing a rate conversion L/M is described wherein data is input to the SRC at an input rate (“Fin”) and output from the SRC at an output rate (“Fout”) equal to Fin*L/M. The SRC includes a low pass filter (“LPF”) including P multiply-add instances, wherein P is a parallelization factor of the SRC; an input formatter for arranging samples received at the SRC in accordance with the rate conversion L/M and providing P*Tpp input samples to the filter at a given time, wherein Tpp is a number of taps per phase of the LPF; and a coefficient bank for storing a plurality of coefficients and for providing P*Tpp of the coefficients to the LPF at a given time.

Abstract: A sample rate converter (“SRC”) for implementing a rate conversion L/M is described wherein data is input to the SRC at an input rate (“Fin”) and output from the SRC at an output rate (“Fout”) equal to Fin*L/M. The SRC includes a low pass filter (“LPF”) including P multiply-add instances, wherein P is a parallelization factor of the SRC; an input formatter for arranging samples received at the SRC in accordance with the rate conversion L/M and providing P*Tpp input samples to the filter at a given time, wherein Tpp is a number of taps per phase of the LPF; and a coefficient bank for storing a plurality of coefficients and for providing P*Tpp of the coefficients to the LPF at a given time.

Abstract: A pipelined video pre-processor includes a plurality of configurable image-processing modules. The modules may be configured using direct processor control, DMA access, or both. A block-control list, accessible via DMA, facilitates configuration of the modules in a manner similar to direct processor control. Parameters in the modules may be updated on a frame-by-frame basis.