Abstract: A DRAM memory cell includes one transistor and one capacitor surrounded by an isolating region. A first electrode of the transistor is formed at the center of the memory cell in a major surface of a substrate. A gate electrode of the transistor is formed on the major surface of the substrate around the first electrode. The capacitor is formed around the gate electrode of the transistor, and may include, as one electrode thereof, a second electrode of the transistor. Various embodiments are described, some including formation of certain of the memory cell elements in a trench in the major surface of the substrate. As a result, current leakage is prevented, capacitor holding time is improved and transistor threshold voltage may be made more stable.