Abstract: Technologies for plasma oxidation protection during hybrid bonding of semiconductor devices includes forming a blocking layer on a metallic bonding pad formed in a bonding surface of a semiconductor device to be bonded and performing a surface treatment on the bonding surface to increase the bonding strength of the bonding surface and contemporaneously remove the blocking layer from the metallic bonding pad. In an illustrative embodiment, the blocking layer is embodied as a self-assembled monolayer (SAM), and the surface treatment is embodied as a surface activation plasma (SAP) treatment. A diffusion barrier layer, such as a silicon carbon nitride layer, may form the bonding surface in some embodiments to reduce diffusion of the metallic bonding pad during an annealing treatment of the bonding process.

Abstract: A method includes providing a first substrate with a first surface including an alkyne moiety. The method includes providing a second substrate with a second surface including an azide moiety. The method further includes bonding the first substrate to the second substrate. The bonding of the first substrate to the second substrate includes making physical contact between the first surface and the second surface at an interface and chemically reacting the alkyne moiety with the azide moiety through a cycloaddition mechanism, thereby forming a triazole moiety-linked layer at the interface.

Abstract: A method for manufacturing semiconductor devices. The method includes placing a semiconductor wafer in a chamber. The method includes applying, in the chamber, a plasma that contains no fluorine. The plasma causes one or more components, in contact with the chamber, that each comprise a fluorinated coating to release its fluorine on a surface of the semiconductor wafer.

Abstract: A method includes providing a first bonding surface on a first substrate, the first bonding surface including a bonding layer that is thermally curable or photocurable. The method includes providing a second bonding surface on a second substrate. The method includes bonding the first substrate to the second substrate by making physical contact between the first bonding surface and second bonding surface. The method further includes applying thermal energy or light to the bonding layer.

Abstract: Devices and methods for forming semiconductor devices are disclosed. The semiconductor device can include a plurality of semiconductor wafers. The plurality of semiconductor wafers can have a dielectric bonding layer disposed thereupon. The dielectric bonding layers can be treated to increase a bonding energy with other semiconductor wafers. A wafer having a treatment applied to a bonding layer can be bonded to another wafer.

Abstract: A method for making forming a semiconductor package comprises forming a plurality of alignment marks in or on a carrier substrate; positioning and bonding a plurality of semiconductor dies to the carrier substrate based on the plurality of alignment marks; further processing the plurality of semiconductor dies into a reconstituted wafer; and decoupling the reconstituted wafer from the carrier substrate at an interface using a laser source. The alignment marks are interposed between the interface and the laser source.

Abstract: Technologies for plasma oxidation protection during hybrid bonding of semiconductor devices includes forming a blocking layer on a metallic bonding pad formed in a bonding surface of a semiconductor device to be bonded and performing a surface treatment on the bonding surface to increase the bonding strength of the bonding surface and contemporaneously remove the blocking layer from the metallic bonding pad. In an illustrative embodiment, the blocking layer is embodied as a self-assembled monolayer (SAM), and the surface treatment is embodied as a surface activation plasma (SAP) treatment. A diffusion barrier layer, such as a silicon carbon nitride layer, may form the bonding surface in some embodiments to reduce diffusion of the metallic bonding pad during an annealing treatment of the bonding process.

Abstract: A semiconductor package is disclosed. The semiconductor package includes a first substrate including a first interconnect structure and a first bonding layer adjacent the first interconnect structure. The semiconductor package includes a second substrate including a second interconnect structure and a second bonding layer adjacent the second interconnect structure. The first bonding layer and second bonding layer each include a metal oxide.

Abstract: A liquid is supplied to a substrate and a chip component is arranged on the liquid. The substrate includes a first surface in which a rectangular mounting region is formed. The chip component includes a second surface having a rectangular shape which substantially coincides with the shape of the mounting region, and has an area substantially equal to that of the mounting region. The mounting region includes first and second regions. Wettability of the first region with respect to the liquid is higher than that of the second region with respect to the liquid. The first region is provided symmetrically with respect to a first central line passing through the middle of a pair of long sides and a second central line passing through the middle of a pair of short sides in the mounting region, and includes rectangular partial regions. The liquid is supplied to the first region.

Abstract: A liquid is supplied to a substrate and a chip component is arranged on the liquid. The substrate includes a first surface in which a rectangular mounting region is formed. The chip component includes a second surface having a rectangular shape which substantially coincides with the shape of the mounting region, and has an area substantially equal to that of the mounting region. The mounting region includes first and second regions. Wettability of the first region with respect to the liquid is higher than that of the second region with respect to the liquid. The first region is provided symmetrically with respect to a first central line passing through the middle of a pair of long sides and a second central line passing through the middle of a pair of short sides in the mounting region, and includes rectangular partial regions. The liquid is supplied to the first region.

Abstract: An imprinting method is capable of separating a molding material and a target material rapidly in pattern formation. The imprinting method includes a transferring process for transferring an inverted pattern of a mold 10 having a desired pattern formed thereon to a resist 30 by pressing the mold 10 against the resist 30; a curing process for curing the resist 30 by heating or irradiating light; and a separating process for separating the mold 10 from the resist 30 after the resist 30 is cured through the transferring process. The separating process includes a pulling process for pulling the mold 10 away from the resist 30 in a direction opposite to a direction in which the resist 30 is pressed; and a pushing process for pushing the resist 30 in the same direction as a direction in which the mold 10 presses the resist 30.

Abstract: In a substrate wiring method, copper is embedded all the way to the lowest parts of a wiring pattern formed on a substrate. The method is used to wire a substrate in a processing chamber kept in a vacuum state, the substrate having a wiring pattern formed thereon. The method includes a preprocessing step in which the wiring pattern on the substrate is cleaned using a desired cleaning gas and an embedding step in which, after the preprocessing step, metal nanoparticles are embedded in the wiring pattern using a clustered metal gas.

Abstract: A substrate cleaning method for cleaning a substrate on which a film is formed with a pattern in a vacuum-state processing chamber includes a preprocessing step where the film formed on the substrate on which the pattern has been formed by an etching process is cleaned by using a cleaning gas; and a consecutive step including an oxidation step where residues attached on a surface of the pattern are oxidized by using an oxidizing gas and a reduction step where the oxidized residues are reduced by using a reducing gas, which are consecutively carried out posterior to the preprocessing step. The gases used in the preprocessing step and the consecutive step are clustered by ejecting the gases into the processing chamber from a gas nozzle whose internal pressure PS is maintained to be higher than an internal pressure PO of the processing chamber.

Abstract: In a substrate wiring method, copper is embedded all the way to the lowest parts of a wiring pattern formed on a substrate. The method is used to wire a substrate in a processing chamber kept in a vacuum state, the substrate having a wiring pattern formed thereon. The method includes a preprocessing step in which the wiring pattern on the substrate is cleaned using a desired cleaning gas and an embedding step in which, after the preprocessing step, metal nanoparticles are embedded in the wiring pattern using a clustered metal gas.

Abstract: An interconnect structure for an integrated circuit and method of forming the interconnect structure. The method includes depositing a metallic layer containing a reactive metal in an interconnect opening formed within a dielectric material containing a dielectric reactant element, thermally reacting at least a portion of the metallic layer with at least a portion of the dielectric material to form a diffusion barrier primarily containing a compound of the reactive metal from the metallic layer and the dielectric reactant element from the dielectric material, and filling the interconnect opening with Cu metal, where the diffusion barrier surrounds the Cu metal within the opening. The reactive metal can be Co, Ru, Mo, W, or Ir, or a combination thereof. The interconnect opening can be a trench, a via, or a dual damascene opening.

Abstract: An imprinting method is capable of separating a molding material and a target material rapidly in pattern formation. The imprinting method includes a transferring process for transferring an inverted pattern of a mold 10 having a desired pattern formed thereon to a resist 30 by pressing the mold 10 against the resist 30; a curing process for curing the resist 30 by heating or irradiating light; and a separating process for separating the mold 10 from the resist 30 after the resist 30 is cured through the transferring process. The separating process includes a pulling process for pulling the mold 10 away from the resist 30 in a direction opposite to a direction in which the resist 30 is pressed; and a pushing process for pushing the resist 30 in the same direction as a direction in which the mold 10 presses the resist 30.

Abstract: A method for integrating metal-containing cap layers into copper (Cu) metallization of semiconductor devices. In one embodiment, the method includes providing a patterned substrate containing metal surfaces and dielectric layer surfaces, and modifying the dielectric layer surfaces by exposure to a reactant gas containing a hydrophobic functional group, where the modifying substitutes a hydrophilic functional group in the dielectric layer surfaces with a hydrophobic functional group. The method further includes depositing metal-containing cap layers selectively on the metal surfaces by exposing the modified dielectric layer surfaces and the metal surfaces to a deposition gas containing metal-containing precursor vapor.

Abstract: Disclosed is a technology in which a nozzle part is mounted in a vacuum chamber and a silicon substrate is held to face a discharge hole of the nozzle part. For example, ClF3 gas and Ar gas are supplied from the nozzle part and the mixed gas is discharged from the nozzle part under a vacuum atmosphere. By doing this, the mixed gas is adiabatically expanded and the Ar atoms or ClF3 molecules are combined, which become a gas cluster. The gas cluster is irradiated to the surface of the silicon substrate without being ionized and, as a result, the surface of the silicon surface becomes a porous state. Then, lithium is grown on the surface of the silicon substrate in a separate vacuum chamber 41 by sputtering without breaking the vacuum.

Abstract: A quantum dot forming method for forming quantum dots on a surface of a substrate includes exciting a substrate surface with a laser beam having a standing wave which is irradiated from one side of the substrate along the surface of the substrate to excite the surface of the substrate at an interval of one half of a wavelength of the standing wave, and forming a quantum dot with a film differing in lattice constant from a base film forming the surface of the substrate by allowing the film differing in lattice constant to grow on the substrate to form the quantum dots in excited spots of the surface of the substrate.

Abstract: A method for integrating metal-containing cap layers into copper (Cu) metallization of semiconductor devices. In one embodiment, the method includes providing a patterned substrate containing metal surfaces and dielectric layer surfaces, and modifying the dielectric layer surfaces by exposure to a reactant gas containing a hydrophobic functional group, where the modifying substitutes a hydrophilic functional group in the dielectric layer surfaces with a hydrophobic functional group. The method further includes depositing metal-containing cap layers selectively on the metal surfaces by exposing the modified dielectric layer surfaces and the metal surfaces to a deposition gas containing metal-containing precursor vapor.