Patents by Inventor Satoki TANIGUCHI

Satoki TANIGUCHI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20260213673
    Abstract: A rectifier includes a first transistor of a drain/source common field effect type and a second transistor of a drain/source common field effect type in which the second transistor is diode-connected to the first transistor so as to allow the first transistor to perform a diode operation, and configures a rectifier stage with the first transistor.
    Type: Application
    Filed: March 16, 2026
    Publication date: July 23, 2026
    Applicant: ROHM CO., LTD.
    Inventors: Satoki TANIGUCHI, Kentaro NASU
  • Patent number: 12603585
    Abstract: A rectifier includes a first transistor of a drain/source common field effect type and a second transistor of a drain/source common field effect type in which the second transistor is diode-connected to the first transistor so as to allow the first transistor to perform a diode operation, and configures a rectifier stage with the first transistor.
    Type: Grant
    Filed: June 8, 2023
    Date of Patent: April 14, 2026
    Assignee: ROHM CO., LTD.
    Inventors: Satoki Taniguchi, Kentaro Nasu
  • Publication number: 20260026329
    Abstract: A semiconductor device includes one and the other wiring groups that are arranged at an interval in a first direction X, the one and the other wiring groups each including first lower wirings and second lower wirings arrayed as stripes extending in the first direction X, a first pad wiring that is arranged over the one and the other wiring groups and is electrically connected to at least one of the first lower wirings of each of the wiring groups, and a second pad wiring that is arranged over the one and the other wiring groups at an interval from the first pad wiring in a second direction Y intersecting the first direction X and is electrically connected to at least one of the second lower wirings of each of the wiring groups.
    Type: Application
    Filed: September 29, 2025
    Publication date: January 22, 2026
    Applicant: ROHM CO., LTD.
    Inventors: Satoki TANIGUCHI, Kentaro NASU, Nozomu NISHIURA, Kohei MORITA
  • Publication number: 20260020325
    Abstract: A semiconductor device includes: a semiconductor chip including a single layer having a first principal surface and a second principal surface on an opposite side to the first principal surface; a first semiconductor region of a first conductivity type formed on the first principal surface side of the semiconductor chip; a second semiconductor region of a second conductivity type formed on the second principal surface side with respect to the first semiconductor region of the semiconductor chip; and a first trench structure including a first trench that penetrates the first semiconductor region from the first principal surface and partitions the first semiconductor region into a first region on one side and a second region on the other side in a cross-sectional view, a control insulating film that covers an inner wall of the first trench, and a control electrode that is embedded in the first trench with the control insulating film interposed therebetween and controls a channel in the second semiconductor regi
    Type: Application
    Filed: September 23, 2025
    Publication date: January 15, 2026
    Applicant: ROHM CO., LTD.
    Inventors: Nozomu NISHIURA, Kentaro NASU, Satoki TANIGUCHI, Kohei MORITA
  • Publication number: 20250301696
    Abstract: A semiconductor device includes a semiconductor chip including first and second main surfaces. A first semiconductor region of a first conductivity type is formed in the semiconductor chip near the first main surface. A second semiconductor region of a second conductivity type is formed closer to the second main surface than the first semiconductor region is. A trench structure includes a trench extending from the first main surface and partitioning the first semiconductor region into first and second regions. A control insulation film covers a wall of the trench. A control electrode is embedded in the trench with the control insulation film interposed to electrically connect the first and second regions. A third semiconductor region of the first conductivity type is formed closer to the second main surface than the second semiconductor region. The third semiconductor region and the trench structure sandwich the second semiconductor region.
    Type: Application
    Filed: March 17, 2025
    Publication date: September 25, 2025
    Applicant: ROHM CO., LTD.
    Inventors: Nozomu NISHIURA, Kentaro NASU, Satoki TANIGUCHI, Kohei MORITA
  • Publication number: 20250294894
    Abstract: A semiconductor chip of a TVS diode includes a first pin junction portion of a first polarity direction and a diode pair region. The diode pair region includes a first reverse pin junction portion of a second polarity direction provided spaced apart from the first pin junction portion in a plan view, and a pn junction portion of the first polarity direction that forms a diode pair with the first reverse pin junction portion. The first pin junction portion includes a p-type first-terminal-side high-concentration region, an n-type first-terminal-side low-concentration region at a position overlapping the first-terminal-side high-concentration region in the plan view, an n-type first-terminal-side contact region, and a p-type first buffer region in contact with the first-terminal-side high-concentration region between the first-terminal-side high-concentration region and the first-terminal-side low-concentration region in a thickness direction of the semiconductor chip.
    Type: Application
    Filed: March 13, 2025
    Publication date: September 18, 2025
    Applicant: ROHM CO., LTD.
    Inventors: Keishi WATANABE, Kentaro WAKI, Satoki TANIGUCHI, Kohei MORITA
  • Publication number: 20250290232
    Abstract: A resin sheet is provided that provide both light-weight properties and mechanical strength using a thermoplastic resin with high deflection temperature under load. The resin sheet is formed from a thermoplastic resin, including: a core layer being a foam resin layer; and skin layers located outward of the core layer as determined along the thickness direction, the core and skin layers forming a continuity. The core layer includes a region A1 and regions A2 each located between the region A1 and the associated skin layer. The regions A2 has a lower average porosity than the region A1, the average porosity being lower than 50%. The thermoplastic resin has a deflection temperature under load not lower than 90° C. The resin sheet has a thickness of 1 to 40 mm. Each skin layer has a thickness of 5 to 50% of the thickness of the resin sheet.
    Type: Application
    Filed: June 4, 2025
    Publication date: September 18, 2025
    Applicant: MAXELL, LTD.
    Inventors: Atsushi YUSA, Kei MIZUTANI, Satoshi YAMAMOTO, Toshiharu GOTO, Satoki TANIGUCHI
  • Publication number: 20250294891
    Abstract: A semiconductor chip of a TVS diode includes a first surface and a second surface at aside opposite the first surface. The semiconductor chip includes first and second pin junctions fora first polarity direction, and a diode-paired region. The diode-paired region includes a high-concentration region of a first conductance type, first and second low-concentration regions that have a lower impurity concentration than the high-concentration region, an isolation region isolating the first and second low-concentration regions, first and second contact regions of a second conductance type, and an internal region of the second conductance type contacting the high-concentration region and arranged closer to the second surface than the high-concentration region. The internal region is arranged overlapping both the first and second low-concentration regions in plan view.
    Type: Application
    Filed: March 11, 2025
    Publication date: September 18, 2025
    Applicant: ROHM CO., LTD.
    Inventors: Keishi WATANABE, Kentaro WAKI, Satoki TANIGUCHI, Kohei MORITA
  • Publication number: 20250267954
    Abstract: A semiconductor device includes: a semiconductor layer of a first conductivity type having a main surface; a first diffusion region of a second conductivity type formed in a surface layer portion of the main surface; a second diffusion region of the first conductivity type formed in the surface layer portion of the main surface; an insulating layer formed on the main surface so as to cover the first diffusion region and the second diffusion region; a first pad disposed on the insulating layer and electrically connected to the first diffusion region; and an internal parasitic capacitance formation portion formed in a surface layer portion of the semiconductor layer and forming an internal parasitic capacitance between a facing portion in the semiconductor layer that faces the first pad with the insulating layer interposed therebetween and the main surface or an extended surface flush with the main surface.
    Type: Application
    Filed: February 14, 2025
    Publication date: August 21, 2025
    Applicant: ROHM CO., LTD.
    Inventors: Kohei MORITA, Satoki TANIGUCHI, Kentaro NASU, Keishi WATANABE, Kentaro WAKI
  • Publication number: 20250267953
    Abstract: A semiconductor device includes: a first diffusion region of an n-type formed in a surface layer portion of a first main surface; a second diffusion region of a p-type formed in the surface layer portion of the first main surface; an insulating layer formed on the first main surface to cover the first diffusion region and the second diffusion region; a first pad disposed on the insulating layer and electrically connected to the first diffusion region; and an internal parasitic capacitance former formed in the surface layer portion of the first main surface to face the first pad with the insulating layer interposed therebetween, wherein the first pad forms a parasitic capacitance, which is connected in series to an internal parasitic capacitance, at a location between the first pad and the insulating layer.
    Type: Application
    Filed: February 14, 2025
    Publication date: August 21, 2025
    Applicant: ROHM CO., LTD.
    Inventors: Kohei MORITA, Satoki TANIGUCHI, Kentaro NASU, Keishi WATANABE, Kentaro WAKI
  • Publication number: 20250018692
    Abstract: A co-extruded sheet reduces swelling and/or cracking of the surface occurring during thermal shaping such as vacuum forming and provides improved mechanical strength. A co-extruded sheet contains a polycarbonate resin, and includes a core layer formed from a foam resin and skin layers formed from a non-foaming resin. The skin layer is laminated to one major surface of the core layer, while the skin layer is laminated to the other major surface of the core layer. The core layer has an expansion ratio of 1.6 to 3. The co-extruded sheet has a thickness of 1 to 5 mm and satisfies expression (1): 0.10? (t1+t2)/T?0.5. In expression (1), t1 indicates the thickness of the skin layer, t2 indicates the thickness of the second skin layer, and T indicates the thickness of the co-extruded sheet.
    Type: Application
    Filed: March 29, 2023
    Publication date: January 16, 2025
    Applicant: MAXELL, LTD.
    Inventors: Satoki TANIGUCHI, Atsushi YUSA, Satoshi YAMAMOTO, Toshiharu GOTO, Kei MIZUTANI
  • Publication number: 20250010589
    Abstract: A co-extruded sheet reduces swelling and/or cracking of the surface occurring during thermal shaping such as vacuum forming and provides improved mechanical strength. A co-extruded sheet contains a polycarbonate resin, and includes a core layer formed from a foam resin and skin layers formed from a non-foaming resin. The skin layer is laminated to one major surface of the core layer, while the skin layer is laminated to the other major surface of the core layer. The co-extruded sheet has a density of 0.4 to 0.9 g/cm3. The co-extruded sheet has a thickness of 1 to 5 mm and satisfies expression (1): 0.10?(t1+t2)/T?0.5. In expression (1), t1 indicates the thickness of the skin layer, t2 indicates the thickness of the second skin layer, and T indicates the thickness of the co-extruded sheet.
    Type: Application
    Filed: October 21, 2022
    Publication date: January 9, 2025
    Applicant: MAXELL, LTD.
    Inventors: Satoki TANIGUCHI, Atsushi YUSA, Satoshi YAMAMOTO, Toshiharu GOTO, Kei MIZUTANI
  • Publication number: 20240014108
    Abstract: A semiconductor device includes a first lead, a second lead spaced apart from the first lead in a first direction, a first semiconductor element on the first lead, a second semiconductor element on the second lead, and a sealing resin covering the first lead, the second lead, the first semiconductor element and the second semiconductor element. The first and second semiconductor elements respectively have first and second element side surfaces facing with each other in the first direction. The sealing resin has a first-direction middle plane equidistant from the first and the second element side surfaces in the first direction. The first lead includes a first main part, and the second lead includes a second main part. The first and the second main parts are spaced apart from each other with reference to the first-direction middle plane.
    Type: Application
    Filed: September 26, 2023
    Publication date: January 11, 2024
    Inventors: Satoki TANIGUCHI, Kentaro NASU, Yoshiaki OCHI
  • Publication number: 20230421072
    Abstract: A rectifier includes a first transistor of a drain/source common field effect type and a second transistor of a drain/source common field effect type in which the second transistor is diode-connected to the first transistor so as to allow the first transistor to perform a diode operation, and configures a rectifier stage with the first transistor.
    Type: Application
    Filed: June 8, 2023
    Publication date: December 28, 2023
    Applicant: ROHM CO., LTD.
    Inventors: Satoki TANIGUCHI, Kentaro NASU
  • Publication number: 20230112317
    Abstract: A resin sheet is provided that provide both light-weight properties and mechanical strength using a thermoplastic resin with high deflection temperature under load. The resin sheet is formed from a thermoplastic resin, including: a core layer being a foam resin layer; and skin layers located outward of the core layer as determined along the thickness direction, the core and skin layers forming a continuity. The core layer includes a region A1 and regions A2 each located between the region A1 and the associated skin layer. The regions A2 has a lower average porosity than the region A1, said average porosity being lower than 50%. The thermoplastic resin has a deflection temperature under load not lower than 90° C. The resin sheet has a thickness of 1 to 40 mm. Each skin layer has a thickness of 5 to 50% of the thickness of the resin sheet.
    Type: Application
    Filed: October 7, 2022
    Publication date: April 13, 2023
    Applicant: MAXELL, LTD.
    Inventors: Atsushi YUSA, Kei MIZUTANI, Satoshi YAMAMOTO, Toshiharu GOTO, Satoki TANIGUCHI
  • Publication number: 20180329238
    Abstract: Provided are a liquid crystal molecule orientation control method and a liquid crystal device which render it possible to change the orientation of liquid crystal molecules without using an electric field. In controlling the orientation of liquid crystal molecules 103a, which are contained in a liquid crystal material 103 sandwiched between alignment films 104, by the liquid crystal molecule orientation control method, an ultrasonic wave is generated in a piezoelectric material 102 so as to propagate to the liquid crystal material 103, and static pressure is generated in accordance with the ultrasonic wave, with the result that the orientation is changed in accordance with the magnitude of the static pressure.
    Type: Application
    Filed: October 12, 2016
    Publication date: November 15, 2018
    Applicant: THE DOSHISHA
    Inventors: Daisuke KOYAMA, Satoki TANIGUCHI, Yuki SHIMIZU