Patents by Inventor Satoko Iida

Satoko Iida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11973096
    Abstract: The present technology relates to a solid-state imaging element, a solid-state imaging element package, and electronic equipment that can suppress occurrence of flares. The solid-state imaging element includes an effective pixel region and a peripheral circuit region. The effective pixel region includes a plurality of pixels arranged two-dimensionally in a matrix pattern. The peripheral circuit region is provided around the effective pixel region. The effective pixel region has a pixel-to-pixel light-shielding film formed at boundary portions between the pixels. In a region on a substrate where a rib structure is formed within the peripheral circuit region, no light-shielding film is formed in the same layer as the pixel-to-pixel light-shielding film. The present technology is applicable, for example, to a solid-state imaging element package including a cover glass that protects a light-receiving surface of the solid-state imaging element.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: April 30, 2024
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Satoko Iida, Tomohiko Asatsuma
  • Patent number: 11902679
    Abstract: An imaging element according to an embodiment includes: a unit pixel including a first pixel having a first photoelectric conversion element and including a second pixel having a second photoelectric conversion element, the second pixel being arranged adjacent to the first pixel; and an accumulation portion that accumulates a charge generated by the second photoelectric conversion element and converts the accumulated charge into a voltage. The accumulation portion is disposed at a boundary between the unit pixel and another unit pixel adjacent to the unit pixel.
    Type: Grant
    Filed: December 8, 2020
    Date of Patent: February 13, 2024
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Tomohiko Asatsuma, Ryosuke Nakamura, Satoko Iida, Koshi Okita
  • Patent number: 11855108
    Abstract: A solid-state imaging element which detects visible light and ultraviolet light in one pixel provides improved resolution. First and second photoelectric conversion elements each perform photoelectric conversion of incident light. A first accumulation part accumulates electric charges that are photoelectrically converted by the first photoelectric conversion element second accumulation part is disposed on one face of a substrate and accumulates electric charges that are photoelectrically converted by the second photoelectric conversion element. A connection part is connected to the second accumulation part and transfers the electric charges accumulated in the second accumulation part to another face of the substrate.
    Type: Grant
    Filed: September 2, 2019
    Date of Patent: December 26, 2023
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Satoko Iida, Yoshiaki Kitano, Kengo Nagata, Toshiaki Ono, Tomohiko Asatsuma
  • Publication number: 20230403483
    Abstract: Imaging elements and imaging devices are disclosed. In one example, a potential of a charge retaining unit that retains a charge generated by photoelectric conversion is adjusted. An imaging element includes a photoelectric conversion unit, a charge retaining unit, a charge transfer unit, a reset unit, an image signal generating unit that generates an image signal, capacitive coupling wiring, and a potential adjustment unit. The capacitive coupling wiring is different from wiring that transmits control signals of the charge transfer unit, the reset unit, and the image signal generating unit and wiring that transmits a generated image signal and is capacitively coupled to the charge retaining unit. The potential adjustment unit applies an adjustment signal for adjusting the potential of the charge retaining unit via the capacitive coupling wiring.
    Type: Application
    Filed: December 17, 2021
    Publication date: December 14, 2023
    Inventors: Yuki Hattori, Satoko Iida
  • Publication number: 20230299113
    Abstract: Provided is a solid-state imaging device that allows high saturation and maximum transfer performance to be achieved. The solid-state imaging device includes a plurality of unit pixels arranged in a two-dimensional array. The plurality of unit pixels each includes a photoelectric conversion unit that photoelectrically converts incident light and a wiring layer stacked on a surface opposite to a light-incident side surface of the photoelectric conversion unit and having a detection node that detects charge stored at the photoelectric conversion unit. In at least some of the plurality of unit pixels, a center of the detection node is coincident with a light receiving center of the photoelectric conversion unit.
    Type: Application
    Filed: July 2, 2021
    Publication date: September 21, 2023
    Inventors: SATOKO IIDA, YUKI HATTORI, YOSHIMITSU NAKASHIMA
  • Publication number: 20230254602
    Abstract: An imaging element according to an embodiment includes: a unit pixel including a first pixel having a first photoelectric conversion element and including a second pixel having a second photoelectric conversion element, the second pixel being arranged adjacent to the first pixel; and an accumulation portion that accumulates a charge generated by the second photoelectric conversion element and converts the accumulated charge into a voltage. The accumulation portion is disposed at a boundary between the unit pixel and another unit pixel adjacent to the unit pixel.
    Type: Application
    Filed: April 13, 2023
    Publication date: August 10, 2023
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Tomohiko ASATSUMA, Ryosuke NAKAMURA, Satoko IIDA, Koshi OKITA
  • Publication number: 20230224602
    Abstract: A solid-state imaging device includes a photoelectric converter, a transfer gate transistor, and an overflow gate transistor. The photoelectric converter is provided in a semiconductor substrate and generates photocharge. The transfer gate transistor is provided at a surface of the semiconductor substrate as a vertical transistor and reads the photocharge stored in the photoelectric converter. The overflow gate transistor is provided at the surface of the semiconductor substrate as a planar transistor and transfers the photocharge overflowing from the photoelectric converter.
    Type: Application
    Filed: March 29, 2021
    Publication date: July 13, 2023
    Inventor: SATOKO IIDA
  • Publication number: 20230018370
    Abstract: An imaging element according to an embodiment includes: a unit pixel including a first pixel having a first photoelectric conversion element and including a second pixel having a second photoelectric conversion element, the second pixel being arranged adjacent to the first pixel; and an accumulation portion that accumulates a charge generated by the second photoelectric conversion element and converts the accumulated charge into a voltage. The accumulation portion is disposed at a boundary between the unit pixel and another unit pixel adjacent to the unit pixel.
    Type: Application
    Filed: December 8, 2020
    Publication date: January 19, 2023
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Tomohiko ASATSUMA, Ryosuke NAKAMURA, Satoko IIDA, Koshi OKITA
  • Patent number: 11509842
    Abstract: Provided is a solid-state imaging element configured to automatically extend dynamic range for each unit pixel. A solid-state imaging element includes, for a unit pixel, a first photoelectric conversion element, a first accumulation portion that accumulates electric charge obtained by photoelectric conversion by the first photoelectric conversion element, and a first film that is electrically connected to the first accumulation portion and has an optical characteristic changing according to applied voltage. Furthermore, the unit pixel of the solid-state imaging element can further include a first transfer transistor that transfers electric charge obtained by photoelectric conversion by the photoelectric conversion element to the first accumulation portion, an amplification transistor that is electrically connected to the first accumulation portion, and a selection transistor that is electrically connected to the amplification transistor.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: November 22, 2022
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Toshiaki Ono, Satoko Iida, Tomohiko Asatsuma, Yoshiaki Kitano, Yusuke Matsumura, Ryoko Kajikawa
  • Publication number: 20220038648
    Abstract: Degradation of image quality is suppressed. A solid-state imaging device according to an embodiment includes: a plurality of first photoelectric conversion elements having a first sensitivity; a plurality of second photoelectric conversion elements having a second sensitivity lower than the first sensitivity; a plurality of charge storage regions that stores charge generated by each of the plurality of second photoelectric conversion elements; a plurality of first color filters; and a plurality of second color filters. In each of the plurality of first photoelectric conversion elements, the second color filter for the second photoelectric conversion element included in the charge storage region closest to the first photoelectric conversion element transmit a wavelength component identical to that of the first color filter for the first photoelectric conversion element closest to the charge storage region.
    Type: Application
    Filed: November 14, 2019
    Publication date: February 3, 2022
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Satoko IIDA, Atsushi SUZUKI, Yorito SAKANO
  • Publication number: 20210343771
    Abstract: The present technology relates to a solid-state imaging element, a solid-state imaging element package, and electronic equipment that can suppress occurrence of flares. The solid-state imaging element includes an effective pixel region and a peripheral circuit region. The effective pixel region includes a plurality of pixels arranged two-dimensionally in a matrix pattern. The peripheral circuit region is provided around the effective pixel region. The effective pixel region has a pixel-to-pixel light-shielding film formed at boundary portions between the pixels. In a region on a substrate where a rib structure is formed within the peripheral circuit region, no light-shielding film is formed in the same layer as the pixel-to-pixel light-shielding film. The present technology is applicable, for example, to a solid-state imaging element package including a cover glass that protects a light-receiving surface of the solid-state imaging element.
    Type: Application
    Filed: October 11, 2019
    Publication date: November 4, 2021
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Satoko IIDA, Tomohiko ASATSUMA
  • Publication number: 20210202545
    Abstract: A solid-state imaging element which detects visible light and ultraviolet light in one pixel provides improved resolution. First and second photoelectric conversion elements each perform photoelectric conversion. of incident light. A first accumulation part accumulates electric charges that are photoelectrically converted by the first photoelectric conversion element. second accumulation part is disposed on one face of a substrate and accumulates electric charges that are photoelectrically converted by the second photoelectric conversion element. A connection part is connected to the second accumulation part and transfers the electric charges accumulated in the second accumulation part to another face of the substrate.
    Type: Application
    Filed: September 2, 2019
    Publication date: July 1, 2021
    Inventors: SATOKO IIDA, YOSHIAKI KITANO, KENGO NAGATA, TOSHIAKI ONO, TOMOHIKO ASATSUMA
  • Patent number: 11039099
    Abstract: An increase in memory capacity is suppressed in a solid-state imaging element that performs correlated double sampling processing. A pixel circuit sequentially generates each of a predetermined reset level and a plurality of signal levels corresponding to the exposure amount. An analog-to-digital converter converts a predetermined reset level into digital data and outputs the data as reset data, converts each of the plurality of pieces of signal data into digital data, and outputs the data as signal data. An arithmetic circuit holds a difference between the reset data and the signal data output first, as held data in a memory, and then adds the held data and the signal data output second and subsequent times together and causes the memory to hold the added data as new held data.
    Type: Grant
    Filed: October 10, 2017
    Date of Patent: June 15, 2021
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Masaki Sakakibara, Yorito Sakano, Satoko Iida
  • Patent number: 10917591
    Abstract: The present disclosure relates to a solid-state imaging device and a method of controlling a solid-state imaging device, and an electronic device for enabling appropriate expansion of a dynamic range with respect to an object moving at a high speed or an object having a large luminance difference between bright and dark to reduce motion distortion (motion artifact). Exposure of a plurality of pixels is individually controlled in units of pixels. The present disclosure can be applied to a solid-state imaging device.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: February 9, 2021
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Satoko Iida, Masaki Sakakibara, Yorito Sakano, Naosuke Asari, Masaaki Takizawa, Tomohiko Asatsuma, Shogo Furuya
  • Patent number: 10868056
    Abstract: The present disclosure relates to a solid-state imaging element and an electronic apparatus which are capable of utilizing almost all photoelectrically converted charges for signals during high capacitance. A pixel includes a selection transistor that is disposed on a drain side of an amplification transistor and selects a read-out row, the selection transistor selects the read-out row after reset by a reset transistor, and a transfer transistor performs reference potential read-out during high capacitance prior to reference potential read-out during low capacitance. For example, the present disclosure is applicable to a lamination-type solid-state imaging element.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: December 15, 2020
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Yoshiaki Tashiro, Satoko Iida, Yorito Sakano
  • Publication number: 20200260026
    Abstract: Provided is a solid-state imaging element configured to automatically extend dynamic range for each unit pixel. A solid-state imaging element includes, for a unit pixel, a first photoelectric conversion element, a first accumulation portion that accumulates electric charge obtained by photoelectric conversion by the first photoelectric conversion element, and a first film that is electrically connected to the first accumulation portion and has an optical characteristic changing according to applied voltage. Furthermore, the unit pixel of the solid-state imaging element can further include a first transfer transistor that transfers electric charge obtained by photoelectric conversion by the photoelectric conversion element to the first accumulation portion, an amplification transistor that is electrically connected to the first accumulation portion, and a selection transistor that is electrically connected to the amplification transistor.
    Type: Application
    Filed: October 12, 2018
    Publication date: August 13, 2020
    Inventors: TOSHIAKI ONO, SATOKO IIDA, TOMOHIKO ASATSUMA, YOSHIAKI KITANO, YUSUKE MATSUMURA, RYOKO KAJIKAWA
  • Publication number: 20200066773
    Abstract: The present disclosure relates to a solid-state imaging element and an electronic apparatus which are capable of utilizing almost all photoelectrically converted charges for signals during high capacitance. A pixel includes a selection transistor that is disposed on a drain side of an amplification transistor and selects a read-out row, the selection transistor selects the read-out row after reset by a reset transistor, and a transfer transistor performs reference potential read-out during high capacitance prior to reference potential read-out during low capacitance. For example, the present disclosure is applicable to a lamination-type solid-state imaging element.
    Type: Application
    Filed: November 30, 2017
    Publication date: February 27, 2020
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Yoshiaki TASHIRO, Satoko IIDA, Yorito SAKANO
  • Publication number: 20200029036
    Abstract: The present disclosure relates to a solid-state imaging device and a method of controlling a solid-state imaging device, and an electronic device for enabling appropriate expansion of a dynamic range with respect to an object moving at a high speed or an object having a large luminance difference between bright and dark to reduce motion distortion (motion artifact). Exposure of a plurality of pixels is individually controlled in units of pixels. The present disclosure can be applied to a solid-state imaging device.
    Type: Application
    Filed: March 30, 2018
    Publication date: January 23, 2020
    Inventors: SATOKO IIDA, MASAKI SAKAKIBARA, YORITO SAKANO, NAOSUKE ASARI, MASAAKI TAKIZAWA, TOMOHIKO ASATSUMA, SHOGO FURUYA
  • Publication number: 20190273883
    Abstract: An increase in memory capacity is suppressed in a solid-state imaging element that performs correlated double sampling processing. A pixel circuit sequentially generates each of a predetermined reset level and a plurality of signal levels corresponding to the exposure amount. An analog-to-digital converter converts a predetermined reset level into digital data and outputs the data as reset data, converts each of the plurality of pieces of signal data into digital data, and outputs the data as signal data. An arithmetic circuit holds a difference between the reset data and the signal data output first, as held data in a memory, and then adds the held data and the signal data output second and subsequent times together and causes the memory to hold the added data as new held data.
    Type: Application
    Filed: October 10, 2017
    Publication date: September 5, 2019
    Inventors: MASAKI SAKAKIBARA, YORITO SAKANO, SATOKO IIDA
  • Patent number: 9437764
    Abstract: An exemplary embodiment is a photoelectric conversion device having a photoelectric conversion portion, and a transfer portion. The transfer portion transfers charges of the photoelectric conversion portion. The photoelectric conversion portion includes first and second semiconductor regions of a first conductivity type. Charges generated by photoelectric conversion are accumulated in the first and second semiconductor regions. According to the structure of the first and second semiconductor regions of the exemplary embodiment or the method for manufacturing them, the transfer efficiency of charges can be improved while improving the sensitivity of the photoelectric conversion portion.
    Type: Grant
    Filed: June 9, 2014
    Date of Patent: September 6, 2016
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Takanori Watanabe, Takafumi Miki, Satoko Iida, Masahiro Kobayashi, Junji Iwata