Patents by Inventor Satoko Nakamura

Satoko Nakamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Imaging element, imaging element driving method, and electronic device
    Patent number: 11991463
    Abstract: An imaging element according to an embodiment includes: a unit pixel including a first pixel having a first photoelectric conversion element and including a second pixel having a second photoelectric conversion element, the second pixel being arranged adjacent to the first pixel; and an accumulation portion that accumulates a charge generated by the second photoelectric conversion element and converts the accumulated charge into a voltage. The accumulation portion is disposed at a boundary between the unit pixel and another unit pixel adjacent to the unit pixel.
    Type: Grant
    Filed: April 13, 2023
    Date of Patent: May 21, 2024
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Tomohiko Asatsuma, Ryosuke Nakamura, Satoko Iida, Koshi Okita
  • Cache memory control apparatus and processor
    Patent number: 6981103
    Abstract: A cache memory control apparatus (20) that may control a cache memory (100) has been disclosed. Cache memory control apparatus (20) may include a control section (21). When a cache miss occurs, a refill request for a line (118) of data may be executed. In response to the refill request, control section (21) may perform control to make a valid bit (103) and a TAG portion (102), corresponding to line (118) of data to be refilled, invalid. This may occur while accessing the address corresponding to the cache miss from an external memory (200). In this way, if a reset occurs during the refill operation, a cache memory control apparatus (20) may recover a cache memory to a state before resetting in a reduced time period. Upon completion of the refill operation, valid bit (103) and TAG portion (102) may be updated.
    Type: Grant
    Filed: June 10, 2002
    Date of Patent: December 27, 2005
    Assignee: NEC Electronics Corporation
    Inventor: Satoko Nakamura
  • Cache memory control apparaus and processor
    Publication number: 20020188810
    Abstract: A cache memory control apparatus (20) that may control a cache memory (100) has been disclosed. Cache memory control apparatus (20) may include a control section (21). When a cache miss occurs, a refill request for a line (118) of data may be executed. In response to the refill request, control section (21) may perform control to make a valid bit (103) and a TAG portion (102), corresponding to line (118) of data to be refilled, invalid. This may occur while accessing the address corresponding to the cache miss from an external memory (200). In this way, if a reset occurs during the refill operation, a cache memory control apparatus (20) may recover a cache memory to a state before resetting in a reduced time period. Upon completion of the refill operation, valid bit (103) and TAG portion (102) may be updated.
    Type: Application
    Filed: June 10, 2002
    Publication date: December 12, 2002
    Inventor: Satoko Nakamura