Patents by Inventor Satoru Ejiri

Satoru Ejiri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7826361
    Abstract: The block #1 capsules a user IP layer by a UDP/IPv6, as well as detecting a destination IP address and specifying a QoS class from a DSCP embedded in a TOS field of an IP header of the user IP layer to transfer data to the block #2 through a UDP port correlated to a corresponding link. The blocks #2 and #3 execute processing of protocols divided into functional blocks with respect to a payload part of a UDP packet obtained from each UDP port to transfer the data to its subsequent block through a UDP port correlated to a corresponding link. The block #4 embeds, into a TOS field of an IP header of an IP packet obtained from each link, a DSCP value of a QoS class correlated to the link.
    Type: Grant
    Filed: April 6, 2004
    Date of Patent: November 2, 2010
    Assignee: NEC Corporation
    Inventor: Satoru Ejiri
  • Publication number: 20060203754
    Abstract: The block #1 capsules a user IP layer by a UDP/IPv6, as well as detecting a destination IP address and specifying a QoS class from a DSCP embedded in a TOS field of an IP header of the user IP layer to transfer data to the block #2 through a UDP port correlated to a corresponding link. The blocks #2 and #3 execute processing of protocols divided into functional blocks with respect to a payload part of a UDP packet obtained from each UDP port to transfer the data to its subsequent block through a UDP port correlated to a corresponding link. The block #4 embeds, into a TOS field of an IP header of an IP packet obtained from each link, a DSCP value of a QoS class correlated to the link.
    Type: Application
    Filed: April 6, 2004
    Publication date: September 14, 2006
    Inventor: Satoru Ejiri
  • Publication number: 20050265366
    Abstract: A method comprising performing an authentication between a communication terminal and a gateway via a first Internet protocol (IP) network according to a configuration method. Configuration data and an IP address belonging to a second IP network is issued from the gateway to the communication terminal. The second IP network is connected with the gateway.
    Type: Application
    Filed: May 25, 2005
    Publication date: December 1, 2005
    Inventor: Satoru Ejiri
  • Patent number: 6834082
    Abstract: An image transmitting system which maintains the same image resolution even when a line speed is set to a low speed. The image transmitting system basically comprises an image data conversion block, a quantization block, a variable-length coding block, smoothing buffers, output selectors, and a dequantization block. The image data conversion block converts input image data into a coefficient suitable for coding. The quantization block quantizes the coefficients obtained through conversion. The variable-length coding block codes the quantized coefficients. The first smoothing buffer smoothes the generated amount of data with respect to a first frame in a block, the second smoothing buffer smoothes the generated amount of data with respect to a second frame in the block, and the third smoothing buffer smoothes the generated amount of data with respect to a third frame in the block.
    Type: Grant
    Filed: December 6, 2000
    Date of Patent: December 21, 2004
    Assignee: NEC Corporation
    Inventors: Satoru Ejiri, Kazuo Ebina
  • Patent number: 6347098
    Abstract: A packet multiplexing apparatus includes at least one high transmission rate data memory for accumulating high transmission rate data, and at least one low transmission rate data memory for accumulating low transmission rate data. A control section determines whether an accumulation quantity of the high transmission rate data reaches a first predetermined value, and issues a transmission instruction when it is determined that the accumulation quantity of the high transmission rate data reaches the first predetermined value. A multiplexing unit multiplexes the high transmission rate data from the high transmission rate data memory and the low transmission rate data from the low transmission rate data memory in response to the transmission instruction to form a packet.
    Type: Grant
    Filed: July 27, 1998
    Date of Patent: February 12, 2002
    Assignee: NEC Corporation
    Inventor: Satoru Ejiri
  • Patent number: 6337867
    Abstract: A multiplexor multiplexing an unlimited number of channels without the load on the multiplexor being increased. This multiplexor has a plurality of one channel encoders, for example four stages of encoders connected in series. When the first encoder is inputted with audio/video data of one channel, the data is inputted from the first encoder to the second encoder at the next stage, multiplexed by audio/video data of one channel inputted to the second encoder and then inputted to the third encoder at the next stage. By repeating this multiplexing, the number of multiplexed channels can be increased, and the load on the multiplexor is not increased because each encoder is inputted only with data for one channel. An abnormality detector is provided for each encoder to release an abnormal encoder from the multiplexor when the encoder's abnormality is detected.
    Type: Grant
    Filed: March 12, 1998
    Date of Patent: January 8, 2002
    Assignee: NEC Corporation
    Inventor: Satoru Ejiri
  • Patent number: 6262990
    Abstract: A fixed length packet multiplexer of low speed universal data having a burst characteristic of different data with different speeds and large speed differences to reduce a transmission delay. In a packet processor, a packet formable time (release timing) is not determined to the time when a predetermined length of payload data are stored in a multiplex buffer like the conventional case. But, a periodic release timing is voluntarily given to a multiplex part from a time generator, and the universal data stored in a buffer for storing the low speed universal data are packeted at the release timing. At this time, when the universal data stored in the buffer are less than the predetermined length of payload data, a stuffing function of a header part of the packet is used to compensate for the data to output the packet. Thus, the release timing cycle is controlled to reduce a multiplex delay.
    Type: Grant
    Filed: December 1, 1998
    Date of Patent: July 17, 2001
    Assignee: NEC Corporation
    Inventor: Satoru Ejiri
  • Publication number: 20010003532
    Abstract: An image transmitting system which maintains the same image resolution even when a line speed is set to a low speed. The image transmitting system basically comprises an image data conversion block, a quantization block, a variable-length coding block, smoothing buffers, output selectors, and a dequantization block. The image data conversion block converts input image data into a coefficient suitable for coding. The quantization block quantizes the coefficients obtained through conversion. The variable-length coding block codes the quantized coefficients. The first smoothing buffer smoothes the generated amount of data with respect to a first frame in a block, the second smoothing buffer smoothes the generated amount of data with respect to a second frame in the block, and the third smoothing buffer smoothes the generated amount of data with respect to a third frame in the block.
    Type: Application
    Filed: December 6, 2000
    Publication date: June 14, 2001
    Applicant: NEC Corporation
    Inventors: Satoru Ejiri, Kazuo Ebina
  • Patent number: 6118317
    Abstract: In the case of sending the sampled clock of transmission coded data together with the coded data and regenerating a clock synchronized with this sampled clock on the receiver side, the drawing-in is speeded up on the received side for the clock information items SCRn sent at unequal intervals. In the case of generating a control voltage of the VCXO in accordance with the received SCRn and the SCCn by the counter, the CPU calculates the amount of frequency fluctuation per unit time and generates a control voltage in accordance with this amount of fluctuation. Thereby, even if SCRn are received at unequal intervals, a rapid follow-up control of the PLL loop including the VCXO becomes possible.
    Type: Grant
    Filed: March 12, 1998
    Date of Patent: September 12, 2000
    Assignee: NEC Corporation
    Inventor: Satoru Ejiri
  • Patent number: 5930451
    Abstract: In an audio and video reproduction system receiving multiplexed data which comprises an audio packet comprising an audio packet header and audio packet data and comprising an audio buffer memory for storing the audio packet data as stored audio data, the audio packet has a plurality of audio rates which correspond to a plurality of rate modes. A detecting block detects a size of the audio packet data as a detected audio data size. A counting block counts the detected audio data size to produce a counted audio data size. A time indication signal generating unit generates a time indication signal by the use of reception system clocks and a time value which is predetermined in relation to the plurality of rate modes. A latching circuit latches the counted audio data size as a latched audio data size on reception of the time indication signal.
    Type: Grant
    Filed: February 19, 1997
    Date of Patent: July 27, 1999
    Assignee: NEC Corporation
    Inventor: Satoru Ejiri