Patents by Inventor Satoru Fukunaga

Satoru Fukunaga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6984586
    Abstract: In a method of thinning a semiconductor wafer, a protection tape smaller in size than the semiconductor wafer is applied to a front of the semiconductor wafer, and a back of the semiconductor wafer is etched. In the etching process, a chemical liquid falls down from the semiconductor wafer without being accumulated on the protection tape because the protection tape is smaller in size than the semiconductor wafer.
    Type: Grant
    Filed: December 13, 2002
    Date of Patent: January 10, 2006
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Noriki Iwasaki, Satoru Fukunaga, Tadayuki Into
  • Publication number: 20030082915
    Abstract: In a method of thinning a semiconductor wafer, a protection tape smaller in size than the semiconductor wafer is applied to a front of the semiconductor wafer, and a back of the semiconductor wafer is etched. In the etching process, a chemical liquid falls down from the semiconductor wafer without being accumulated on the protection tape because the protection tape is smaller in size than the semiconductor wafer.
    Type: Application
    Filed: December 13, 2002
    Publication date: May 1, 2003
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Noriki Iwasaki, Satoru Fukunaga, Tadayuki Into
  • Patent number: 6520844
    Abstract: In a method of thinning a semiconductor wafer, a protection tape smaller in size than the semiconductor wafer is applied to a front of the semiconductor wafer, and a back of the semiconductor wafer is etched. In the etching process, a chemical liquid falls down from the semiconductor wafer without being accumulated on the protection tape because the protection tape is smaller in size than the semiconductor wafer.
    Type: Grant
    Filed: May 30, 2001
    Date of Patent: February 18, 2003
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Noriki Iwasaki, Satoru Fukunaga, Tadayuki Into
  • Patent number: 6423102
    Abstract: A jig used for assembling semiconductor devices has an arrangement wherein the first semiconductor integrated circuit chip, which is die-bonded and wire-bonded onto one surface of a lead frame, is fitted to the inner section of a support stage and is supported by an elastic member that is designed to be higher than the inner section, while the lead frame is supported by the outer section of the support stage. In this state, the second semiconductor integrated circuit chip is die-bonded onto the other surface of the lead frame by applying pressure by means of a bonding collet. Thus, it becomes possible to prevent cracks that may be caused in a passivation film and also to improve the reliability and the final yield of semiconductor devices.
    Type: Grant
    Filed: December 9, 1997
    Date of Patent: July 23, 2002
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Satoru Fukunaga, Hiroyuki Nakanishi
  • Publication number: 20020016135
    Abstract: In a method of thinning a semiconductor wafer, a protection tape smaller in size than the semiconductor wafer is applied to a front of the semiconductor wafer, and a back of the semiconductor wafer is etched. In the etching process, a chemical liquid falls down from the semiconductor wafer without being accumulated on the protection tape because the protection tape is smaller in size than the semiconductor wafer.
    Type: Application
    Filed: May 30, 2001
    Publication date: February 7, 2002
    Inventors: Noriki Iwasaki, Satoru Fukunaga, Tadayuki Into
  • Patent number: 5412314
    Abstract: A package tester includes an inlet station for arranging a test board in which package sockets mounting packages are disposed in one or plural lines for performing package test by flowing an electric current through the package and transmitting signals to the package, the package being composed of parts including electric parts or electronic parts and being sequentially formed on a package tape, an inlet pusher for pushing the test board mounting the packages by a width of the test board in a feeding direction of the test board from the inlet station to the package socket, a conveyor for receiving the test board sequentially pushed out of the inlet station by the inlet pusher and conveying the received test board to a testing area, a contact device opposed to the conveyor and capable of being electrically connected to the test board arranged on the conveyor, an outlet station receiving the test board sequentially pushed out of the conveyor by sequentially pushing-out of the test board by means of the inlet pu
    Type: Grant
    Filed: January 22, 1993
    Date of Patent: May 2, 1995
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Satoru Fukunaga, Junichirou Hisatomi, Kazuhiro Nakamura, Ken'ichi Ohi, Hideki Tanaka, Masayuki Tabuchi
  • Patent number: 5247248
    Abstract: In order to improve the operability of a burn-in apparatus, to shorten the operating time, to reduce the number of the components, and to increase the package density of semiconductor integrated circuits to be accommodated within a burn-in apparatus, semiconductor integrated circuits with a lead frame are mounted on a first wiring board by means of fixing the pressuring member to the first wiring board with a magnetic force. Thereafter, the first wiring board is mounted to a second wiring board, and both are to be inserted into a burn-in apparatus.
    Type: Grant
    Filed: February 7, 1992
    Date of Patent: September 21, 1993
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Satoru Fukunaga