Abstract: The weight of a body-to-be-conveyed constituting a conveying device is reduced, and the friction force between the sliding surface of the body-to-be-conveyed and the conveyance path is reduced. A body-to-be-conveyed that is a component of a conveying device that uses electromagnetic force as thrust and can move in a horizontal direction includes a mover in which a bottom surface is arranged so that a predetermined gap is formed in a vertical direction with respect to the sliding surface thereof, in which the mover includes a permanent magnet and a cover, a gap facing surface of the permanent magnet facing the gap includes one magnetic pole, the cover is installed on a side of the permanent magnet opposite from the gap facing surface in the vertical direction, the horizontal outermost diameter of the cover is larger than the horizontal outermost diameter of the permanent magnet, and the cover is formed of a flat plate.

Abstract: The present invention controls liquid shaking during transportation while maintaining high-precision with respect to the stopping position of a specimen at the time of device start-up.

Abstract: The present invention provides a transport device and a specimen analysis system including the transport device that reduce the pulsation of thrust for moving an object to be transported, reduce vibration of the object to be transported during transport, and realize stable transport. The transport device of the present invention includes a first electromagnet unit including a first tooth made of a magnetic body, a first core connected to the first tooth and made of a magnetic body, and a first winding formed around the first core; a second electromagnet unit including a second tooth installed adjacent to the first electromagnet unit and made of a magnetic body, a second core connected to the second tooth and made of a magnetic body, a second winding formed around the second core; and a magnetic coupling unit made of a magnetic body between the first tooth of the first electromagnet unit and the second tooth of the second electromagnet unit.

Abstract: A video provision apparatus (10) includes a specification unit (11) for acquiring a racer ID for identifying a racer specified by a user from among racers that participate in a race, a video collection unit (12) for collecting videos of the race captured in the same time section from a plurality of cameras, a generation unit (15) for generating, based on the racer ID specified by the user, a user-specific video from the videos collected from the plurality of cameras, and an output control unit (16) for causing a user terminal used by the user to output the user-specific video.

Abstract: A semiconductor memory device includes a memory cell, a sense amplifier connected to the memory cell, a first data latch that is connected to the sense amplifier and stores data of the memory cell, a second data latch that is connected to the sense amplifier and stores data of the memory cell, a third data latch that is connected to an input/output circuit, a fourth data latch that is connected to the input/output circuit, a first data bus of n-bit width that connects the sense amplifier, the first data latch, and the second data latch, and a second data bus of m-bit width that connects the third data latch and the fourth data latch to the first data bus, where m<n.

Abstract: A composite type thin-film magnetic head. In one embodiment, a substrate is used as a base, and an insulating film, a lower shielding magnetic film, a magneto-resistive element, an upper shielding magnetic film, a magnetic gap film, a recording inductive magnetic film and a protective layer are laminated on this base. An inductive head used for recording is formed by the upper shielding magnetic film. A magnetic gap film, a recording inductive magnetic film, and a magneto-resistive head used for playback are formed by the magneto-resistive element. The upper shielding magnetic film and recording inductive magnetic film are formed by an electroplating of permalloy. The upper shielding magnetic film has a lower nickel concentration on the side of the magnetic gap film than on the side of the magneto-resistive element.

Abstract: A semiconductor memory device includes normal row selection lines (NWL1 to NWL128) for selecting one of normal rows, a spare row selection line (SWL) for selecting a spare row instead when one of the normal rows has a defect, fuses (F1 to F128) which are respectively arranged on the normal row selection lines, and blown when a defect exists, a normal row non-selection circuit (inverters IN3 and IN6 and gate G3) when one of the fuses (F1 to F128) is blown, setting a corresponding normal row in a non-selected state, and a spare row selection circuit (gates G4, G5, and G6, transistors P2 and N1, a NOR gate NR1, and an inverter IN6) selecting the spare row instead of the defective normal row. The spare row selection circuit performs dynamic operation in synchronism with a clock (ck).

Abstract: In an asynchronous type memory device for controlling a plurality of bytes independently, even if the byte control signal changes in the write cycle, the automatic power-down can be released and further the data can be read after data have been written. When data are transferred from the input/output terminals I/OUBm and I/OLBn to the internal data buses DbusUB and DbusLB through the upper byte data input buffers DinUBm and the lower byte input buffers DinLBn, the change detecting sections UWTD and LWTD generate the write start synchronous pulse .phi.BWS and the write end synchronous pulse .phi.BWE on the basis of the logical result of the write request signal /WE and the control signal /UB or /LB. Therefore, when the data are written and read for each byte independently, data can be written in and read from the memory cells irrespective of the data conditions. Further, the written data can be read immediately without changing the addresses.

Abstract: A plurality of voltage supply circuits each including an inverter circuit are provided at the final stage of a row decoder. The voltage supply circuits are supplied with voltage Vdd and voltage Vxx. The voltage Vxx is set at a level of Vss in a normal operation mode and at a level higher than that of Vdd in a burn-in test mode. In the latter mode, the voltage Vdd is applied to the voltage supply circuit connected to a selected word line, while the voltage Vxx (higher than Vdd) is applied to the voltage supply circuit connected to a nonselected word line. All word lines are therefore set at a high level and rendered in a selective state.

Abstract: In a CMOS type static RAM, a substrate bias voltage VPP higher than a power supply voltage supplied from an outer unit is supplied to an N type substrate region of a PMOS transistor of a CMOS inverter forming a word line driving circuit to bias the N type substrate region to the bias voltage VPP and to a power supply terminal of the CMOS inverter as a power supply voltage. Whereby, resistance of storage data to incidence of radioactive rays is increased just after writing to a storage node of a memory cell is ended, and a soft error generation rate can be easily reduced.

Abstract: A semiconductor memory device including: a memory cell array having at least one cell array unit, the cell array unit including a plurality of memory cells; a decoder for selecting at least one the memory cell in accordance with an externally supplied address; an input/output terminal for outputting data read from the selected memory cell and for receiving data supplied externally and sending the data to the selected memory cell; at least one data line for connecting the input/output terminal to each the cell array unit; sense amplifiers serially connected to each the data line in a multiple stage configuration for amplifying the read data; a write buffer connected in parallel with one of the sense amplifiers connected to each data line; by-pass switching elements connected between input and output terminals of the other sense amplifiers connected to each the data line; and a control circuit for applying an on-signal to at least one by-pass switching element when writing data, the on-signal turning on at leas

Abstract: In a data read circuit, for a semiconductor storage device, data of a memory cell (11) selected according to an address is inputted to a sense amplifier (22) via a pair of complementary first data lines (N1 to N6). The sense amplifier outputs the inputted and amplified data to a pair of complementary second data lines (N7, N8). First switching means (Tr3) equalizes the pair of complementary first data lines (N5, N6) at the input side of the sense amplifier (22) by making the first data lines conductive with respect to each other. Second switching means (Tr4) equalizes the pair of complementary second data lines (N7, N8) by making the second data lines conductive with respect to each other. Third switching means (Tr5, Tr6) equalizes by making the pair of first data lines (N5, N6) at the input side of the sense amplifier (22) and corresponding ones of the pair of second data lines (N7, N8) conductive with respect to each other. Second equalizing pulse generator means (42) generates a second equalizing pulse (.