Patents by Inventor Satoru Ishizaka

Satoru Ishizaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11889616
    Abstract: In a circuit board (700A), a first capacitor (410) extends from a wiring pattern (110) to a region located on one side of the wiring pattern (110) in the width direction. A second capacitor (420) extends from the wiring pattern (110) to a region located on the other side of the wiring pattern (110) in the width direction. With a semiconductor device (300) mounted on the circuit board (700A), a power supply terminal (320) is electrically connected to the wiring pattern (110). The semiconductor device (300), the wiring pattern (110), the first capacitor (410), a first interlayer joint (510), a ground plane (210), and a third interlayer joint (530) constitute a first closed circuit. The semiconductor device (300), the wiring pattern (110), the second capacitor (420), a second interlayer joint (520), the ground plane (210), and the third interlayer joint (530) constitute a second closed circuit.
    Type: Grant
    Filed: March 9, 2021
    Date of Patent: January 30, 2024
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Masatoshi Toyonaga, Satoru Ishizaka
  • Publication number: 20230403785
    Abstract: In a circuit board (700A), a first capacitor (410) extends from a wiring pattern (110) to a region located on one side of the wiring pattern (110) in the width direction. A second capacitor (420) extends from the wiring pattern (110) to a region located on the other side of the wiring pattern (110) in the width direction. With a semiconductor device (300) mounted on the circuit board (700A), a power supply terminal (320) is electrically connected to the wiring pattern (110). The semiconductor device (300), the wiring pattern (110), the first capacitor (410), a first interlayer joint (510), a ground plane (210), and a third interlayer joint (530) constitute a first closed circuit. The semiconductor device (300), the wiring pattern (110), the second capacitor (420), a second interlayer joint (520), the ground plane (210), and the third interlayer joint (530) constitute a second closed circuit.
    Type: Application
    Filed: March 9, 2021
    Publication date: December 14, 2023
    Applicant: Mitsubishi Electric Corporation
    Inventors: Masatoshi TOYONAGA, Satoru ISHIZAKA
  • Publication number: 20220245311
    Abstract: A design support system includes variable extraction means and setting means. In the design support system, the variable extraction means extracts from verified design data a variable that defines design constraint. The setting means sets the design constraint by analyzing, using statistical processing or machine learning, a frequency distribution of the variable extracted by the variable extraction means.
    Type: Application
    Filed: August 31, 2020
    Publication date: August 4, 2022
    Applicant: Mitsubishi Electric Corporation
    Inventors: Satoru ISHIZAKA, Yuji NAOMI
  • Patent number: 10608657
    Abstract: An AD conversion apparatus includes an AD conversion unit; a reference voltage switching unit that is disposed between an output of a sensor and an analog input terminal of the AD conversion unit and is connectable to the output of the sensor and a plurality of reference voltage lines; and a control unit to control switching the reference voltage input to the AD conversion unit by connecting the reference voltage switching unit to one of the reference voltage lines and to the output of the sensor. An analog output value of the sensor is input to the analog input terminal of the AD conversion unit via the reference voltage switching unit and is converted into a digital value.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: March 31, 2020
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Takahiro Ito, Satoru Ishizaka, Keiji Ninomiya
  • Publication number: 20190253065
    Abstract: An AD conversion apparatus includes an AD conversion unit; a reference voltage switching unit that is disposed between an output of a sensor and an analog input terminal of the AD conversion unit and is connectable to the output of the sensor and a plurality of reference voltage lines; and a control unit to control switching the reference voltage input to the AD conversion unit by connecting the reference voltage switching unit to one of the reference voltage lines and to the output of the sensor. An analog output value of the sensor is input to the analog input terminal of the AD conversion unit via the reference voltage switching unit and is converted into a digital value.
    Type: Application
    Filed: October 28, 2016
    Publication date: August 15, 2019
    Applicant: Mitsubishi Electric Corporation
    Inventors: Takahiro ITO, Satoru ISHIZAKA, Keiji NINOMIYA
  • Publication number: 20190172622
    Abstract: A power supply device for an ozone generator, which supplies electric power to the ozone generator, is configured such that: a transformer, an inverter, and a reactor are disposed inside of one housing; a flat heat exchanger which cools passing air with cooling water is disposed at a lower part inside of the housing; the transformer and the inverter are disposed above the heat exchanger; the reactor is disposed above the transformer and the inverter; a protection panel is disposed further toward the front side of the housing than the transformer and the inverter by being separated from a front door of the housing; and cooling air is circulated in the housing by means of a fan that disposed at a position inside of the front door.
    Type: Application
    Filed: August 9, 2016
    Publication date: June 6, 2019
    Applicant: Mitsubishi Electric Corporation
    Inventors: Daisuke TAKAUCHI, Yoshiaki ODAI, Hajime NAKATANI, Toshihiro YOSHIDA, Takashi KUMAGAI, Kenji SHIMOHATA, Satoru ISHIZAKA, Taichiro TAMIDA
  • Patent number: 10177761
    Abstract: A digital output circuit to be driven by an insulated power-supply circuit includes a transistor to turn on/off an external power supply in accordance with a signal output by a light receiving element in an insulating circuit in response to a signal processed by a controller. The external supply is connected to an output device. The output circuit includes a switching unit having first and second mechanisms to switch each of wires between a connected state and a non-connected state at two places between the light receiving element and the source or emitter of the transistor, and a logic adjusting unit to adjust inversion of a logic output of the light receiving element in correspondence to the type of the transistor, such that the output circuit is switched between a sink-current type and a source-current type.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: January 8, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Hiroki Shionoya, Satoru Ishizaka, Hisashi Hirokawa, Seigo Inobe
  • Publication number: 20180337673
    Abstract: A digital output circuit to be driven by an insulated power-supply circuit includes a transistor to turn on/off an external power supply in accordance with a signal output by a light receiving element in an insulating circuit in response to a signal processed by a controller. The external supply is connected to an output device. The output circuit includes a switching unit having first and second mechanisms to switch each of wires between a connected state and a non-connected state at two places between the light receiving element and the source or emitter of the transistor, and a logic adjusting unit to adjust inversion of a logic output of the light receiving element in correspondence to the type of the transistor, such that the output circuit is switched between a sink-current type and a source-current type.
    Type: Application
    Filed: January 30, 2015
    Publication date: November 22, 2018
    Applicant: Mitsubishi Electric Corporation
    Inventors: Hiroki SHIONOYA, Satoru ISHIZAKA, Hisashi HIROKAWA, Seigo INOBE
  • Patent number: 10084618
    Abstract: A transmission circuit, mounted on a printed board and having attenuation characteristics, to attenuate an amplitude of a reception signal according to the attenuation characteristics, and to transmit the amplitude-attenuated reception signal, as an attenuation signal; and a correction circuit, mounted on the printed board and having correction characteristics, to attenuate an attenuation signal that has been received from the transmission circuit according to the correction characteristics, and to transmit the attenuation signal attenuated, as a correction signal are provided. The attenuation characteristics are such characteristics that the ratio of the amplitude of the attenuation signal to the amplitude of the reception signal decreases as the frequency of the reception signal increases. The correction characteristics are characteristics with which the ratio of the amplitude of the correction signal to the amplitude of the attenuation signal increases as the frequency of the attenuation signal increases.
    Type: Grant
    Filed: March 20, 2014
    Date of Patent: September 25, 2018
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Satoru Ishizaka, Yoshiyuki Kusano, Takahiro Ito, Yoshimitsu Tawarayama
  • Patent number: 9655270
    Abstract: An electronic device comprises a plurality of printed circuit boards having signal GNDs, a metal bar which electrically connects to the respective signal GNDs of the plurality of printed circuit boards, and a card basket which houses the plurality of printed circuit boards and the metal bar and serves as a frame GND. The electronic device also comprises a dielectric between the card basket and the metal bar. The metal bar, the card basket, and the dielectric constitute a noise control capacitor having specific frequency characteristics. By the specific frequency characteristics, the noise control capacitor releases electromagnetic noise occurring in the respective signal GNDs to an outside and shields external noise generated outside.
    Type: Grant
    Filed: October 22, 2012
    Date of Patent: May 16, 2017
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Hiroyuki Kimata, Satoru Ishizaka, Toshio Anzai, Keita Fujimaru, Yoko Toda
  • Publication number: 20170005837
    Abstract: A transmission circuit, mounted on a printed board and having attenuation characteristics, to attenuate an amplitude of a reception signal according to the attenuation characteristics, and to transmit the amplitude-attenuated reception signal, as an attenuation signal; and a correction circuit, mounted on the printed board and having correction characteristics, to attenuate an attenuation signal that has been received from the transmission circuit according to the correction characteristics, and to transmit the attenuation signal attenuated, as a correction signal are provided. The attenuation characteristics are such characteristics that the ratio of the amplitude of the attenuation signal to the amplitude of the reception signal decreases as the frequency of the reception signal increases. The correction characteristics are characteristics with which the ratio of the amplitude of the correction signal to the amplitude of the attenuation signal increases as the frequency of the attenuation signal increases.
    Type: Application
    Filed: March 20, 2014
    Publication date: January 5, 2017
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Satoru ISHIZAKA, Yoshiyuki KUSANO, Takahiro ITO, Yoshimitsu TAWARAYAMA
  • Patent number: 9453868
    Abstract: When static electrical charge by electromagnetic waves is applied to a test-target board or test noises are applied to the ground of the test-target board, a test device tests as to whether or not noises are conducted through a path from an OUT terminal of an amplifier circuit to the ground of the test-target board, and a test device tests as to whether or not noises are conducted through a path from an OUT terminal of an amplifier circuit to the ground of the test-target board together with the number of conductions.
    Type: Grant
    Filed: March 23, 2012
    Date of Patent: September 27, 2016
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Hiroyuki Kimata, Satoru Ishizaka
  • Publication number: 20150342078
    Abstract: An electronic device comprises a plurality of printed circuit boards having signal GNDs, a metal bar which electrically connects to the respective signal GNDs of the plurality of printed circuit boards, and a card basket which houses the plurality of printed circuit boards and the metal bar and serves as a frame GND. The electronic device also comprises a dielectric between the card basket and the metal bar. The metal bar, the card basket, and the dielectric constitute a noise control capacitor having specific frequency characteristics. By the specific frequency characteristics, the noise control capacitor releases electromagnetic noise occurring in the respective signal GNDs to an outside and shields external noise generated outside.
    Type: Application
    Filed: October 22, 2012
    Publication date: November 26, 2015
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Hiroyuki KIMATA, Satoru ISHIZAKA, Toshio ANZAI, Yoko TODA
  • Publication number: 20150241495
    Abstract: When static electrical charge by electromagnetic waves is applied to a test-target board or test noises are applied to the ground of the test-target board, a test device tests as to whether or not noises are conducted through a path from an OUT terminal of an amplifier circuit to the ground of the test-target board, and a test device tests as to whether or not noises are conducted through a path from an OUT terminal of an amplifier circuit to the ground of the test-target board together with the number of conductions.
    Type: Application
    Filed: March 23, 2012
    Publication date: August 27, 2015
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Hiroyuki Kimata, Satoru Ishizaka
  • Patent number: 8072288
    Abstract: A directional coupler capable of improving a directionality of a directional coupler body including four terminals. The directional coupler includes a directional coupler body including the four terminals of an input port, an output port, a coupling port, and an isolation port; and a combiner for combining powers of an output signal of the coupling port and an output signal of the isolation port of the directional coupler body; and a directionality improving circuit for amplifying or attenuating at least one of the output signal of the coupling port and the output signal of the isolation port before outputting the same, and the combiner combines powers of the output signals amplified or attenuated by the directionality improving circuit.
    Type: Grant
    Filed: April 11, 2008
    Date of Patent: December 6, 2011
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kazuhisa Yamauchi, Masatoshi Nakayama, Yasuhiro Onaka, Tomokazu Hamada, Satoru Ishizaka
  • Publication number: 20100097160
    Abstract: A directional coupler capable of improving a directionality of a directional coupler body including four terminals. The directional coupler includes a directional coupler body including the four terminals of an input port, an output port, a coupling port, and an isolation port; and a combiner for combining powers of an output signal of the coupling port and an output signal of the isolation port of the directional coupler body; and a directionality improving circuit for amplifying or attenuating at least one of the output signal of the coupling port and the output signal of the isolation port before outputting the same, and the combiner combines powers of the output signals amplified or attenuated by the directionality improving circuit.
    Type: Application
    Filed: April 11, 2008
    Publication date: April 22, 2010
    Applicant: Mitsubishi Electric Corporation
    Inventors: Kazuhisa Yamauchi, Masatoshi Nakayama, Yasuhiro Onaka, Tomokazu Hamada, Satoru Ishizaka
  • Patent number: 7649412
    Abstract: When an input signal level is small, the electrical length of a phase line 21 and the electrical length of a phase line 23 are set in such a manner that the impedance seen by looking into the output side from an impedance reference point 11 at the output side of a carrier amplifier 3 becomes 2R+? (where R is a load resistance and ? is positive), and the electrical length of a phase line 22 is set at a difference between the electrical length of the phase line 21 and the electrical length of the phase line 23.
    Type: Grant
    Filed: July 31, 2006
    Date of Patent: January 19, 2010
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kenichi Horiguchi, Satoru Ishizaka, Kazuhisa Yamauchi, Masatoshi Nakayama
  • Publication number: 20090206926
    Abstract: When an input signal level is small, the electrical length of a phase line 21 and the electrical length of a phase line 23 are set in such a manner that the impedance seen by looking into the output side from an impedance reference point 11 at the output side of a carrier amplifier 3 becomes 2R+? (where R is a load resistance and ? is positive), and the electrical length of a phase line 22 is set at a difference between the electrical length of the phase line 21 and the electrical length of the phase line 23.
    Type: Application
    Filed: July 31, 2006
    Publication date: August 20, 2009
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Kenichi Horiguchi, Satoru Ishizaka, Kazuhisa Yamauchi, Masatoshi Nakayama
  • Patent number: 5452539
    Abstract: A method of carrying rats and an apparatus for trapping rats capable of solving problems of a prior art apparatus by repeatedly using a single carrier during the carriage of a rat. In the course of carrying a rat inside a duct toward a processing site, air flow is generated to move a carrier which pushes and moves the rat to the processing site but the carrier is held so as to be returned to its original position. At this time, another air flow is generate to return the carrier to its original position to prepare for a next trapping operation.
    Type: Grant
    Filed: August 24, 1994
    Date of Patent: September 26, 1995
    Assignee: Ikari Corporation
    Inventors: Toshishige Kurosawa, Satoru Ishizaka, She Rin, Mutsumi Tanaka